Study of Digital Circuit based Linear Feedback Shift Register for VLSI Application
Keywords:
Digital Circuit, LFSR, VLSIAbstract
The design of VLSI testing methodologies needs to be improved in order to advance VLSI technology. Randomization and sampling are necessary to enhance the controllability and observability of testing methods. Test techniques should cover at least 90% of legitimate fault inclusion. Replication can be used to test VLSI circuits with more than 20,000 ports. The probability of undetected legitimate faults needs to be further reduced. To make VLSI inspection simple and risk-free, certain guidelines must be included when tracing test paths. For high-quality VLSI test planning, factors such as test strategy, initialization, synchronous system behavior, scan mode logic, complex wired logic, signal flow, single-shot clock testing, clock testing, power-on reset, and issues in similar modules must be taken into account. The test strategy must be selected during the design phase. A VLSI circuit must be driven from a known state in order to be examined. Sequential circuits such as shift registers, counters, latches, and registers are activated in response to a reset signal; for optimal testing, they must be loaded with preliminary values. A separate control circuit should be used to load these initial values.
References
J. Pekarik et al., “RFCMOS Technology from 0.25 µm to 65 nm: The State of the Art,” CICC, 2014.
Y. Tsividis, Operation and Modeling of the MOS Transistor, Oxford University Press.
C. Chen, J. W. Chou, W. Lur, and S. W. Sun, “A Novel 0.25 µm Shallow Trench Isolation Technology,” Electron Devices Meeting, 1996, pp. 837–840, Dec. 2006.
G. Scott et al., “NMOS drive current reduction caused by transistor layout and trench isolation induced stress,” Electron Devices Meeting 1999 – IEDM Technical Digest, International, pp. 827–830, 5–8 Dec. 2009.
Andrew M. Abo and Paul R. Gray, “A 1.5-V 10-bit 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE Journal of Solid-State Circuits, May 2019.
R. G. H. Eschauzier and J. H. Huijsing, Frequency Compensation Techniques for Low-Power Operational Amplifiers, Boston: MA-Kluwer, 2015.
J. H. Huijsing, R. Hogervorst, and K. J. de Langen, “Low-power low-voltage VLSI operational amplifier cells,” IEEE Transactions on Circuits and Systems I, vol. 42, pp. 841–852, Nov. 2015.
Ivonne Di Sancarlo, Dario Giotta, Andrea Baschirotto, and Richard Gaggl, “A 65-nm 84-dB-gain 200-MHz-UGB CMOS fully differential three-stage amplifier with a novel common-mode control,” ESSCIRC, pp. 341–347, 15–19 Sept. 2018.
A. Ghadiri and H. Mahmoodi-Meimand, “Comparative energy and delay of energy recovery and square wave clock flip-flops for high-performance and low power applications,” Proc. International Conference on Microelectronics, pp. 89–92, 2013.
P. Zhao, T. Darwish, and M. Bayoumi, “Low power and high speed explicit-pulsed flip-flops,” Proc. Midwest Symposium on Circuits and Systems, pp. 477–480, 2012.
N. Nedovic, M. Aleksic, and V. G. Okladzija, “Conditional techniques for low power consumption flip-flops,” Proc. International Conference on Electronics, Circuits and Systems, pp. 803–806, 2011.
Sainiranjan Musakayala and Ovais Shah, “An Effective Sleep State Approach in Low Leakage Power VLSI Design,” International Research Journal of Engineering and Technology, vol. 03, May 2016.
Subrat Mahalik and Bhanu Teja, “Leakage Power Reduction in CMOS VLSI,” International Journal of Engineering Research & Technology, vol. 03, May 2014.
Chanchal Kumar, Avinash Sharan Mishra, and Vijay Kumar Sharma, “Leakage Power Reduction in CMOS Logic Circuits Using Stack ON/OFF Technique,” in Proc. Second International Conference on Intelligent Computing and Control Systems, 2018.
R. Lorenzo and S. Chaudhury, “LCNT—an approach to minimize leakage power in CMOS integrated circuits,” Microsystem Technologies, vol. 23, no. 9, pp. 4245–4253, 2017.
Downloads
How to Cite
Issue
Section
License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
