Vol. 8 No. 4 (2020): Volume 08 Issue 04 October - December 2020

Original Research Articles

• IMPLIMENATION OF FM0/MANCHESTER ENCODING USING SOLS TECHNIQUES-A Review

  ROHINI

  1-6

  • 181
  • Pdf ¹⁷

• Design and Stability of Voltage-Modulated Direct Power Control for Weak Grid Connected Voltage Source Inverters

  Ms. Kadam Pooja Babasaheb, Prof. Dr. B.M. Patil

  17-25

  • 263
  • Pdf ¹⁹

• AN EXPERIMENTAL INVESTIGATION ON PARTIAL REPLACEMENT OF FINE AGGREGATE WITH BOTTOM ASH AND QUARRY DUST

  PAMARTHI PURNA MUNINDRA, PILLI NARENDRA BABU

  26-32

  • 81
  • Pdf ¹¹

• Optimization of transients and FFT of SCMOS Memory Sense Amplifiers for DRAM using 300nm

  Sarvesh Tripathi, Dr. Neetesh Raghuwanshi, Dr. Bharti Chourasia

  33-38

  • 22
  • pdf ⁷

• Efficient Time and Power of 9/7 Coefficient based 2-D Discrete Wavelet Transform using Vedic Math’s

  Roshni Singh, Prof. Sunny Jain

  33-43

  • 38
  • pdf ⁷

• A Survey of True Single Phase Clocking Flip-Flop in Different CMOS Technology

  Shahna Khan, Prashant Purohit

  44-48

  • 77
  • pdf ¹⁰

• Dedicated Short Range Communication Techniques

  Rohini

  51-57

  • 118
  • pdf ⁷

• A Review paper On Fruit/Leaf/Plant Disease Detection Using various Image Processing Approaches

  Rupesh Kumar, Suresh S. Gawande, Satyarth Tiwari

  58-63

  • 194
  • pdf ¹²

• To study, analysis and implementation of Fruit/Leave Disease Detection using image processing and neural approach

  Rupesh Kumar, Suresh S. Gawande, Satyarth Tiwari

  64-71

  • 68
  • pdf ¹⁰

• High Speed Area Efficient VLSI Architecture for Adaptive Filter using Multi-Rate Approach

  Sourabh Rai, Prof. Kamna Mishra

  72-75

  • 68
  • pdf ⁶

• Analysis of VLSI Architecture For AI Based 1D/2D wavelet filter using Daub-6 Wavelet Filter

  M.Mercy Parimala

  76-84

  • 29
  • pdf ¹¹

• Design, Implementation and Fast Fourier Analysis of Digital Locked loops for clock generation using C5 SCMOS

  Aditya Pratap Singh, Prof. Satyarth Tiwari

  85-90

  • 123
  • pdf ¹¹

• Study of Design and Implementation of PLL clock generator

  Aditya Pratap Singh, Prof. Satyarth Tiwari

  91-94

  • 28
  • pdf ¹⁰

• Anti- Forensics of Median Filtered Image using Non-Linear Optimization Techniques

  Seema, Ms. Swati Gupta, Mr. Bijender Bansal, Dr. Deepak Goyal, Dr. Monika Goyal

  95-102

  • 76
  • pdf ¹²

• An Overview And Review On Multiplier In VHDL

  KM Sarvesh, Suresh Gawande

  10-3-110

  • 60
  • pdf ¹⁵

• Comparative Analysis Of Micropipelined Multiplier With Carry Select Adder

  KM Sarvesh, Suresh Gawande

  111-119

  • 43
  • pdf ⁷

• Comparison Of Double Warren And K-Type Steel Truss Bridge For Weight Subjected To Double Track Railway Loading

  Mahesh Thakare, P. R Barbude

  120-123

  • 43
  • pdf ²²

• A Review on Coronavirus Disease a New Threat to Public Health and Strategies for Rational Use of Personal Protective Equipment (PP

  Dimisulu Priyanka, Veluru Sri Devi, R. Srikanth, Venkat Rao Poiba

  124-138

  • 36
  • pdf ⁴

• Improvement in THD and Good Power Factor for Three Phase AC-DC Converter by using PWM and Capacitor Technique

  Pankaj Kumar, Prof. Ashish Bhargav

  139-143

  • 63
  • pdf ⁷

• Spectrum Efficiency and BER Analysis of Beamforming Design for Massive MIMO Systems

  Dorthy Louis, Prof. Satyarth Tiwari, Prof. Suresh. S. Gawande

  144-147

  • 121
  • pdf ⁶

• Review paper on Beamforming Design for Massive MIMO Systems with Channel State Information

  Dorthy Louis, Prof. Satyarth Tiwari, Prof. Suresh. S. Gawande

  148-151

  • 124
  • pdf ⁵

• Implementation on Binary Arithmetic Coders based on MC-DCT for Image Compression on FPGA System

  Neha Shukla, Prof. Suresh. S. Gawande, Prof. Sher Singh

  152-156

  • 51
  • pdf ¹¹

• High Speed Complex Vedic Multiplier using Hybrid Square Brent Kung Adder Technique

  Shivdyal Ram, Ravitesh Mishra, Dr. Sanjeev Gupta

  157-162

  • 125
  • pdf ⁷

• Laboratory Experiment On Mix Design As Per Is Code Using Fiyash And Plasticizer

  Shivani singh baghel, Sandeep K Shrivastava

  163-170

  • 96
  • pdf ¹⁰

• Review Paper of Binary Codes for Error Detection and Correction for FPGA Implementation

  Nidhi Shukla, Prof. Suresh. S. Gawande, Prof. Sher Singh

  171-176

  • 57
  • pdf ⁸

• FPGA Implementation of the CRC using Parallel Pipelining Architecture for Error Detection and Correction

  Nidhi Shukla, Prof. Suresh. S. Gawande, Prof. Sher Singh

  177-181

  • 48
  • pdf ⁹

• FPGA Implementation of Digital IF Filter with Low Complexity and Less Delay using Multi-rate Approach

  Ankesh Singh, Prof. Suresh. S. Gawande, Prof. Sher Singh

  182-185

  • 113
  • pdf ¹⁰

• The Corrosion of Democratic Values Through Criminal Influence in Governance

  Dr. Sanjay Bhardwaj

  186-191

  • 22
  • pdf ²⁴