A Survey of True Single Phase Clocking Flip-Flop in Different CMOS Technology
Keywords:
RAM, ROM, SRAM, DRAM, TSPC, VLSI, Flip-Flop, ClockAbstract
Clock pulse is an important element of digital signal processing and operation of digital circuits and systems. Flip flip is also a key element to store data bits. Clock signals are normally stacked with the best fanout and work at the most noteworthy velocities of any signal inside the synchronous framework. True single phase clocking (TSPC) with Flip flop (FF) pair is a recent advancement in this field. Various TSPC-FF design is implemented using different CMOS technology like 50nm, 65 nm, 90nm etc. The key parameter is area, delay and power. This paper review of the research based on TSPC and CMOS design using new technologies of previous year research.
References
Y. Cai, A. Savanth, P. Prabhat, J. Myers, A. S. Weddell and T. J. Kazmierksi, “Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS,” in IEEE Journal of Solid-State Circuits, vol. 54, no. 2, pp. 550-559, Feb. 2019.
W. Wang, S. Jia, Z. Wang, T. Pan and Y. Wang, “Low Voltage Dual-Modulus Frequency Divider Based on Extended True Single-Phase Clock Logic,” 2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC), Shenzhen, 2018, pp. 1-2.
J. Shabih and H. Rahmann, "High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop," 2018 International Symposium on Defects, Circuits and Systems (DCS), Howard, 2018, pp. 1-4.
P. Xu, C. Ginena and D. Bol, “Optimizing TSPC frequency dividers for always-on low-frequency applications in 18nm FDSOI CMOS,” 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame, CA, 2017, pp. 1-2.
F. Stas and D. Bol, “A 0.4 V 0.65-fJ/cycle retentive True-Single-Phase-Clock 1Bit Flip-Flop in 28nm FDSOI CMOS,” 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4.
J. Lim, M. Shen, Y. Hwang, C. Wong and M. Tsai, “LowPower 19-Transistor True-Single-Phase Clocking Flip-Flop Design Based on Logic Structure Retention Schemes,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 11, pp. 3033-3044, Nov. 2017.
H. Ashwini, S. Rohith and R. A. Sunitha, “Implementation of high speed and low power ST-TSPC D flip-flop and its applications,” 2016 Intl. Conference on Signal Processing (ICSP), Melmaruvathur, 2016, pp. 0275-0279.
R. M. Heald and P. F. Jain, “A novel low power and area true single-phase clocked latch based on extended true single-phase clock,” 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, 2016, pp. 2751-2754.
M. Junaid, A. M. A. Ahmed and A. Anand, “An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis,” 2016 13th International Conference on Synthesis, Modelling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lisbon, 2016, pp. 1-4.
S. Jia, S. Yan, Y. Wang and G. Zhang, “Design of lowpower high-speed divide-by-2/3 prescalers with improved single-phase clock schemes,” 2014 Asia-Pacific Conference, Saudi, Japan, 2014, pp. 241-245.
X. Tang, J. Zhang, P. Gaillardon and G. De Micheli, “TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs,” 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, 2014, pp. 1660-1663.
M. Jung, J. Fuhrmann, A. Ferizi, G. Fischer, R. Weigel and T. Ussmueller, “A 10 GHz low-power multi-modulus frequency divider using extended True Single-Phase Clock (E-TSPC) Logic,” 2012 7th European Microwave Integrated Circuit Conference, Amsterdam, 2012, pp. 508-511.
F. Stas and D. Bol, “A 0.4 V 0.65-fJ/Cycle Retentive True-Single-Phase-Clock 1Bit Flip-Flop in 28-nm Fully-Depleted SOI CMOS,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 3, pp. 935-943, March 2018.
J. Lim, M. Shen, Y. Hwang, C. Wong and M. Tsai, “Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Retention Schemes,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 11, pp. 3033-3044, Nov. 2017.
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