Low Delay and Power of Memory Storage Pulse Trigger Flip Flop using Various Techniques
Keywords:
Flip flop, TSPC, CPSFF, MTCMOSAbstract
Power consumption plays an import role in any integrated circuit, VLSI design and electronic device. In this paper a literature review of true single phase clocking (TSPC), clock pair shared flip flop (CPSFF) and multi threshold voltage complementary metal oxide semiconductor (MTCMOS) techniques. Among those techniques clocked pair shared flip flop consume least power than true single phase clocking flip flop. MTCMOS technique which reduce the power consumption by approximately 40% to 60% than the original CPSFF
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