Implementation on Binary Arithmetic Coders based on MC-DCT for Image Compression on FPGA System
Keywords:
DCT, CORDIC, Shift and Add, Virtex-5, Number of SliceAbstract
In the latter years many of the architectures for discrete cosine transform (DCT) has been suggested and concluded that CORDIC (Coordinate-Rotation-Digital-Computer) processor based design is best suited and convenient for DCT design. CORDIC (Coordinate-Rotation-Digital-Computer) is division of shift and add phenomenon based principle for rotation of vector and rotation of plan, which is mainly used for the calculation of Trigonometric and Hyperbolic operations. CORDIC based architecture delivers iteration method and regulated like digit by digit operation. For these operation, it is pre-owned add, subtract, shifting of given bits and lookup table. Proposed architecture is compromise of input elements adding and subtracting, CORDIC module and output elements. Proposed Architecture is counterfeit for 8-point DCT and synthesized adopting Xilinx FPGA ISI 14.1i Vertex-5 device (xc5vfx100t-3ff1738) as a target device, which can engage at a maximum frequency of 184.556 MHZ.
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