VLSI Architecture for Combined R2B, R4B & R8B FFT using Bidirectional Gate
Keywords:
R₂B, R₄B, R₈B, SDF, FFTAbstract
Fast Fourier Transform (FFT) is a major part in communication modules and DSP processor. FFT includes large number of arithmetic operation during their operation. For each operation it performs large number of switching operations and consumes large amount of delay. Combined R₂B, R₄B & R₈B and bidirectional gate encourages reducing the number of switching activity by reducing the number of operations in FFT. An enhanced combined R₂B, R₄B & R₈B and bidirectional gate is utilized to reduce the number of arithmetic operations in the FFT architecture. The performance of the improved FFT architecture is estimated to find its suitability for the low delay Wireless communication system. An arithmetic operation includes addition, subtraction and multiplication. Each arithmetic operation is designed based on the number of ones and zeros in the input data pattern. Based on the set of input data number of switching operations can be reducing by introducing the enhanced pruning algorithm to the FFT. All design is simulated Xilinx software and calculated simulation parameter i.e. slice, look up table (LUT) and delay.
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