Low Power and High Speed Combined Radix-2, 4 & 8 DIT FFT using Reversible Logic Gate
Keywords:
Adder/ Sub tractor, Reversible Gates, Fast Fourier Transform, DKG Gate, Peres Gate, TR GateAbstract
FFT is normally utilized in computerized flag preparing algorithms. 4G correspondence and different remote framework based correspondence are directly hotly debated issues of innovative work in the remote correspondence and organizing field. FFT is a calculation that speeds up the count of DFT. In the main stage, low multifaceted nature Radix-2 Multi-way Delay Commutator (R2MDC) FFT recurrence change method is created through Exceptionally Large Scale Integration System structure condition. Low power utilization, less zone and rapid are the VLSI primary parameters. Customary R2MDC FFT structure has more equipment multifaceted nature because of its escalated computational components. Two strategies are utilized to plan radix-2 FFT calculation. In firest strategy is plan radix-2 FFT with the help of reversible Peres gate and TR gate. Second method is design radix-2 FFT with the help of reversible DKG Gate. The all structure are usage vertex-4 device family Xilinx programming and looked at past calculation.
References
Shashidhara. K. S and H.C. Srinivasaiah, “Low Power and Area efficient FFT architecture through decomposition technique”, International Conference on Computer Communication and Informatics, pp. 01-06, 2017.
Fahad Qureshi, Jarmo Takala, Anastasia Volkova, Thibault Hilaire, “Multiplierless Unified Architecture for Mixed Radix-2/3/4 FFTs”, 25th European Signal Processing Conference (EUSIPCO), IEEE 2017.
Fahad Qureshi, Muazam Ali, and Jarmo Takala, “Multiplierless Reconfigurable Processing Element for Mixed Radix-2/3/4/5 FFTs”, International Conference on 2017 IEEE.
Ms. A. Anjana and Mrs. A.V Ananthalakshmi, “Design of Reversible 32-Bit BCD Add-Subtract Unit using Parallel Pipelined Method”, International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB16), 2016 IEEE.
Matthew Morrison and Nagarajan Ranganathan, “Design of a Reversible ALU based on Novel Programmable Reversible Logic Gate Structures”, 2015 IEEE Computer Society Annual Symposium on VLSI.
Mr. Abhishek Gupta, Mr. UtsavMalviya and Prof. VinodKapse, “Design of Speed, Energy and Power Efficient Reversible Logic Based Vedic ALU for Digital Processors”, Computer Society Annual Symposium on VLSI, IEEE 2012.
H. Thapliyal and N. Ranganathan, "Design of Efficient Reversible Binary Subtractors Based on A New Reversible Gate," Proc. of the ComputerSociety Annual Symposium on VLSI, IEEE 2009.
M. Morrison and N. Ranganathan, "Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures," IEEE International Symposium on VLSI, pp. 126-131, IEEE 2011.
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