VLSI Architecture for Evaluation of n-bit Universal Linear Feedback Shift Register
Keywords:
Serial in Serial Output (SISO), Serial in parallel out (SIPO), Parallel in Serial out (PISO), Parallel in Parallel out (PIPO), Maximum FrequencyAbstract
Evolution of n-bit linear feedback shift register in very high scale integrated circuit hardware description language (VHDL) and evaluates its performance with respect to logic speed, number of slice and maximum frequency. Structural implementation of linear feedback reversible serial in serial out (SISO), serial in parallel out (SIPO), parallel in serial out (PISO) and parallel in parallel out (PIPO) in VHDL is configurable in terms of different parameter. The target device used for implementation of linear feedback shift register is Xilinx software with Spartan-3 device family. The output waveforms and timing report are also discussed.
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