FPGA Implementation of the CRC using Parallel Pipelining Architecture for Error Detection and Correction
Keywords:
Binary Golay Code (23, 12, 7), Extended Golay Code (24, 12, 8), Adder, Weight Measurement UnitAbstract
VLSI architecture for fast extended Golay encoder and decoder are presented in this paper. The extended golay code encode and decode of the bit is (24, 12, 8) format. The first bit of the format is represent the transmit Golay encoder bit, second bit of the format is represent the polynomial bit and third bit of the format is represent the hamming distance. Extended Golay codes are detection up to eight bit error and correction up to three bits. The extended Golay code is main block of the cyclic redundancy check (CRC). CRC is error detection code commonly used in wireless communication system. The extended Golay code is implemented Xilinx software with vertex-2p device family. The extended Golay code is implemented in term of number of slice, number of LUT and maximum combinational path delay compared with existing Golay code.
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