Implementation of IEEE 754 Floating Point Multiplier using Partition Technique and Ling-Enhance Adder
Keywords:
IEEE754,, Single Precision Floating Point (SP FP), Double Precision Floating Point (DP FP), Binary to Excess-1 ConverterAbstract
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Due to which high speed adder architecture become important. Several adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed IEEE 754 floating point multiplier using carry select adder (CSA). Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family.
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