FPGA Implementation of Optimized Decimal Floating Point Multiplier using Binary Integer Decimal Encoding
Abstract
Binary floating point arithmetic is popularly used in hardware designs. But there are certain flaws in binary floating point arithmetic (BFP) namely; rounding error, error is representing decimal fractions etc. To reduce these errors decimal floating point arithmetic is used. In this paper an optimized approach to implement IEEE complaint binary integer decimal encoding based multiplier unit is presented. The proposed optimizations are given to reduce the delay and dynamic power consumption.
References
M. F. Cowlishaw, “Decimal Floating-Point: Algorism for Computers,” Proceedings of the 16th IEEE Symposium on Computer Arithmetic, June 2003, Santiago de Compostela, Spain, pp. 104-111.
D.G. for Economic and F. A. C. from the Commission to the European Council, “Review of the Introduction of Euro Notes and Coins,” EURO PAPERS, Apr. 2002.
IBM Corporation, “The ‘telco’ benchmark,” Available at http://www2.hursley.ibm.com/decimal/telco.html, 2002.
M. F. Cowlishaw, “The decNumber Library,” Available at http://www2.hursley.ibm.com/decimal/decnumber/pdf, 2006.
Sun Microsystems, “BigDecimal (Java 2 Platforms SE v1.4.0),” URL: http://java.sun/com/products, Sun Microsystems Inc., 2002.
ANSI/IEEE 754-1985, “Standard for Binary Floating-Point Arithmetic.”
http://en.wikipedia.org/wiki/Binary_Integer_Decimal.
P. Tang, “Binary-Integer Decimal Encoding for Decimal Floating-Point,” Intel Corporation, Available at http://754r.ucbtest.org/issues/decimal/bid_rationale.pdf.
M. F. Cowlishaw, “Densely Packed Decimal Encoding,” IEEE Proceedings – Computers and Digital Techniques, vol. 149, May 2002, pp. 102-104.
Ping Tak Peter Tang, “BID – Binary Integer Decimal Encoding,” Intel Corporation, July 2006.
Sonia Gonzalez-Navarro, Charles Tsen, Member, and Michael J. Schulte, “Binary Integer Decimal-Based Floating-Point Multiplication,” IEEE Transactions on Computers, vol. 62, no. 7, July 2013, pp. 1460-1466.
http://www.mitpublications.org/yellow_images/1315565167_logo_13.pdf.
http://www.xilinx.com/support/documentation/white_papers/wp370_Intelligent_Clock_Gating.pdf.
J. Di and J. S. Yuan, “Power-aware Pipelined Multiplier Design Based on 2-Dimensional Pipeline Gating,” in 13th Great Lakes Symposium on VLSI, ACM, 2003, pp. 64–67.
Sunjoo Hong, Taehwan Roh, and Hoi-Jun Yoo, “A 145W 8×8 Parallel Multiplier Based on Optimized Bypassing Architecture,” Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea, IEEE, pp. 1175-1178, 2011.
Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, and Chia-Jen Sheu, “Low Power Multipliers Using Enhanced Row Bypassing Schemes,” Department of Electronic Engineering, National Yunlin University of Science & Technology, Touliu, Yunlin, Taiwan, IEEE, pp. 136-140, 2007.
George Economakos, Dimitris Bekiaris, and Kiamal Pekmestzi, “A Mixed Style Architecture for Low Power Multipliers Based on a Bypass Technique,” National Technical University of Athens, School of Electrical and Computer Engineering, Heroon Polytechniou 9, GR-15780 Athens, Greece, IEEE, pp. 4-6, 2010.
Meng-Lin Hsia and Oscal T.-C. Chen, “Low Power Multiplier Optimized by Partial-Product Summation and Adder Cells,” Department of Electrical Engineering, National Chung Cheng University, Chia-Yi, 621, Taiwan, IEEE, pp. 3042-3045, 2009.
Guy Even, Silvia M. Mueller, Peter-Michael Seidel, “A Dual Precision IEEE Floating-Point Multiplier,” Elsevier INTEGRATION, the VLSI Journal, 29 (2000) 167-180.
Downloads
How to Cite
Issue
Section
License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
