Comparative Analysis Of Micropipelined Multiplier With Carry Select Adder
Keywords:
Multiplier, Carry Select Adder, pipelining, synchronous clock, VHDL modelling, Xilinx14.4.Abstract
In this paper, design of two different multipliers are presented, one by introducing Carry Select Adder (CSLA) in partial product lines and another by synchronous Micro pipeline multiplier. The multipliers presented in this paper were all modelled using Very High Speed Integration Hardware Description Language. The design employs the modified Booth algorithm. A 2-phase micro-pipelined latch controller is used which controls the 4-phase pipeline with standard transparent latches. The comparison is done on the basis of three performance parameters i.e. Area, Speed and Power consumption. Previously in the literature, performance analysis was carried out between multiplier.
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