Optimized Analysis of Reversible ALU based on Arithmetic and Memory Unit
Keywords:
Reversible Gates, Arithmetic Logic Unit, Ancilla Input, DelayAbstract
Reversible computing spans computational models that are both forward and backward deterministic. These models have applications in program inversion and bidirectional computing, and are also interesting as a study of theoretical properties. In this paper, investigate reversible arithmetic logic unit (ALU) computing systems to physical gate-level implementation. Arithmetic operations are a basis for many computing systems, so a proposed the design of adder, sub-tractor, multiplexer, multiplier, comparator and memory element i.e. delay flip flop (D_FF) work towards a reversible circuit. The adder and sub-tractor circuit consist of DKG gate, multiplexer circuit consist of R gate, multiplier consist of toffoli, Peres and HNG gate, comparator consist of BJN gate and D_FF consist of Feynman and Fredkin gate. In all design implemented Xilinx software and simulated VHDL text bench.
References
S. Vijayasharathi, V. Tamilselvan, K. Saranya, J. Harigukmar and L. Sathesakumar, “Optimized Arithmetic and Logical Unit Design using Reversible Logic Gates,” Second International Conference on Applied Artificial Intelligence and Computing (ICAAIC), pp. 1597–1603, IEEE 2023.
Safaeicadeh, B., Mahdjour, E., Haghparast, M., Sayedsaeedi, and Hosseinzadeh, M., “Novel design and simulation of reversible ALU in quantum dot cellular automata,” The Journal of Supercomputing, Vol. 78, Issue 1, pp. 868–882, 2022.
Swathi, M., and Rudra, B., “Implementation of reversible logic gates with quantum gates,” In IEEE 11th annual computing and communication workshop and conference (CCWC), pp. 1557–1563, IEEE 2021.
Bhattacharya, S., and Sen, A., “A Review on Reversible Computing and its applications on combinational circuits,” International Journal, Vol. 9, Issue 6, 2021.
Jeevitha, K., Manju, K., Vijayasharathi, S., “Implementation of deinterleaver in WIMAX using FPGA,” Journal of Advanced Research in Dynamical and Control Systems, Vol. 11, Issue 4, pp. 1211–1217, 2019.
Radha, N., and Maheswari, M., “High speed efficient multiplier design using reversible gates,” In International Conference on Computer Communication and Informatics (ICCCI), pp. 1–4, IEEE 2018.
Dwamyathan, S.M., and Banumathi, V., “Design and analysis of FPGA based 32 bit ALU using reversible gates,” In IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE), pp. 1–4, IEEE 2017.
Shukla, V., Singh, O.P., Mishra, G.R., and Tiwari, R.K., “Design and performance analysis for the reversible realization of adder/subtractor circuit,” In International Conference on Emerging Trends in Computing and Communication Technologies (ICETCCT), pp. 1–6, IEEE 2017.
Shukla, V., Singh, O.P., Mishra, G.R., and Tiwari, R.K., “Design and performance analysis for the reversible realization of adder/subtractor circuit,” In International Conference on Emerging Trends in Computing and Communication Technologies (ICETCCT), pp. 1–6, IEEE 2017.
Siviyasari, T., and Harigukmar, J., “Efficient architecture reverse converter design using fan Carlson structure with carry look ahead adder,” In International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), pp. 1620–1623, IEEE 2016.
Laffa Jamal and Hafiz Md. Hasan Babu, “Design and Implementation of a Reversible Central Processing Unit,” 2015 IEEE Computer Society Annual Symposium on VLSI, 2015 IEEE.
Md. Shamsujjoha and Hafiz Md. Hasan Babu, “A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor,” 2013 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013.
Michael Nachtigall and Nagarajan Ranganathan, “Design and Analysis of a Novel Reversible Encoder/Decoder,” 2011 11th IEEE International Conference on Nanotechnology, Portland Marriott August 15–18, 2011, Portland, Oregon, USA.
Noor Muhammed Nayeem, Md. Adnan Hossain, Md. Mutsimul Haque, Latifa Jamal, Hafiz Md. Hasan Babu, “Novel Reversible Division Hardware,” 978-1-4244-4809-0/09/$25.00 ©2009 IEEE.
Matthew Morrison and Nagarajan Ranganathan, “Design of a Reversible ALU based on Novel Programmable Reversible Logic Structures,” 2013 IEEE Computer Society Annual Symposium on VLSI.
Lekshmi Viswanath and Pomi, M., “Design and Analysis of 16 Bit Reversible ALU,” ISSN: 2278-0661, Volume 1, Issue 1 (May–June 2012), pp. 45–53.
Downloads
How to Cite
Issue
Section
License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
