Delay Efficient VLSI Architecture for Wavelet Decomposition using Complex Multiplier
Keywords:
1_D DWT, 2_D DWT, CMAbstract
In this paper, high performance VLSI architectures for complex multiplier (CM) based 1-D and 2-D Discrete wavelet transforms (DWTs) are proposed. The proposed logic used for area efficient CM based DWT is to perform the whole operation with one processing element. Similarly, the proposed logic used for delay efficient CM based DWT is to perform the whole operation with multiple processing elements in parallel. In both the cases, the processing element consists of one adder and one proposed multiply add design. The proposed and existing design based 1-D and 2-D CM based DWTs are implemented with Xilinx software. The guideline focus of this investigation striving is to decide capable VLSI structures, for the gear use of the 9/7 and 5/3 DWT, using complex multiplier (CM) and improving the speed and hardware complicities of existing plans.
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