VLSI Architecture for 1-D and 2-D DWT using Canonic Signed Digit Technique
Keywords:
1-D DWT, 2-D DWT, CSD, Xilinx SoftwareAbstract
Several architectures have been suggested for efficient VLSI implementation of 2-D DWT for real-time applications. It is found that multipliers consume more chip area and increases complexity of the DWT architecture. Multiplier-less hardware implementation approach provides a solution to reduce chip area, lower hardware-complexity and higher throughput of computation of the DWT architecture. Based on the proposed 1-D & 2-D DWT using canonic signed digit (CSD) are presented in this paper for area-delay efficient realization of multilevel 2-D DWT. We demonstrate that CSD is a very efficient architecture with adders as the main component and free of ROM, multiplication, and subtraction. The simulation was performed using XILINX 14.5i and calculate simulated parameter i.e. number of slice, look up table and delay.
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