Optimization Design of Partition Multiplier based on Brent Kung Adder
Keywords:
Brent Kung Adder, Vedic Multiplier, Delay, Slice Flip Flop, Carry Look Ahead AdderAbstract
In this paper a partition multiplier based on Brent Kung adder is presented. Partition multiplier is used in various applications i.e. wireless communication, image processing and digital signal processing. We have design area efficient partition multiplier with the help of Brent kung adder. All design is implemented VHDL platform and Xilinx 14.2 software. The Brent–Kung adder is a parallel prefix adder (PPA) and is modified form of carry-look ahead adder (CLA). It acquainted higher normality with the structure of the adder and has less wiring issues, reduces complexities, provides better execution and less chip region which is not the case with the Kogge–Stone adder (KSA). It is also very faster than ripple-carry adders (RCA).
References
Ranjan Kumar Barik, Manoranjan Pradhan, Rutuparna Panda, “Time efficient signed Vedic multiplier using redundant binary representation”, Journal Engineering 2017, Vol. 2017, Iss. 3, pp. 60–68.
Basant Kumar Mohanty, and Pramod Kumar Meher, “High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 78, No.06, April 2016.
Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram, “Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 34, Issue 7, 2017.
L khoele phimu and Manoj Kumar, “Design and Implementation of Area Efficient 2-Parallel Filters on FPGA using Image System”, International Conference on Energy, Communication, Data Analytics and Soft Computing, IEEE 2017.
Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner, “FPGA Implementation of High Speed FIR Filters Using Add and Shift Method”, 1-4244-9707-X/06/$20.00 ©2006 IEEE.
Amina Naaz.S, Mr.Pradeep M.N, Satish Bhairannawar and Srinivas halvi, “FPGA Implementation Of High Speed Vedic Multiplier using CSLA For Parallel Fir Architecture”, 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS).
Laxman P. JThakre, Suresh Balpande, Umesh Akare, Sudhir Lande, “Performance Evaluation and Synthesis of Multiplier used in FFT operation using Conventional and Vedic algorithms,” Third international conference on emerging trends in Engineering and Technology , IEEE, 2010.
S. S. Kerur, Prakash Narchi, Jayashree C N, Harish M Kittur and Girish V. A., “Implementation of Vedic Multiplier for Digital Signal Processing,” International Conference on VLSI ,Communication & Instrumentation (ICVCI), 2011.
G. Vaithiyanathan, K. Venkatesan, S.Sivaramakrishnan, S.Sivaand, S. Jayakumar, “Simulation and implementation of Vedic multiplier using VHDL code,” International Journal of Scientific & Engineering Research, vol.4, 2013.
Pushpalata Verma and K. K. Mehta, “Implementation of an Efficient Multiplier based on Vedic Mathematics Using EDA Tool,” International Journal of Engineering and Advanced Technology(IJEAT), vol.1, June 2012.
C. Cheng and K. K. Parhi, “Furthur complexity reduction of parallel FIR filters,” in Proc. IEEE ISCAS, May 2005, vol. 2, pp. 1835–1838.
C. Cheng and K. K. Parhi, “Low-cost parallel FIR structures with 2-stage parallelism,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 2, pp. 280–290, Feb. 2007.
J. G. Chung and K. K. Parhi, “Frequency-spectrum-based low-area low-power parallel FIR filter design,” EURASIP J. Appl. Signal Process., vol. 2002, no. 9, pp. 444–453, Jan. 2002.
K. K. Parhi, VLSI Digital Signal Processing systems: Design and Implementation. New York: Wiley, 1999.
Nivedita A. Pande, Vaishali Niranjane, Anagha V. Choudhari, “Vedic Mathematics for Fast Multiplication in DSP,” International Journal of Engineering and Innovative Technology (IJEIT) ,vol.2, 2013.
Krishnaveni D. and Umarani.T.G, “Vlsi implementation of Vedic multiplier with reduced delay,” International Journal of Scientific & Engineering Research, vol.2, May-2011.
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