Review Paper on VLSI Architecture for 2-D Discrete Wavelet Transform using Multiplier-less Technique

Abstract

This review paper presents a comprehensive analysis of VLSI architectures for implementing the 2-D Discrete Wavelet Transform (DWT) using multiplier-less techniques. The 2-D DWT is a fundamental tool in image processing applications such as compression, denoising, and feature extraction, especially in standards like JPEG2000. However, conventional hardware implementations rely heavily on multipliers, which increase design complexity, area, and power consumption. To overcome these limitations, recent research has focused on multiplier-less approaches that replace complex multipliers with efficient shift-and-add operations, distributed arithmetic, and coefficient approximation methods.

The paper critically examines various existing architectures, including lifting scheme-based designs, distributed arithmetic (DA)-based implementations, and pipeline and parallel processing techniques. These methods significantly reduce hardware utilization while maintaining computational accuracy. The use of efficient adders and memory-based computations further enhances performance by minimizing critical path delay and improving throughput. Additionally, the review highlights trade-offs between area, speed, and power consumption across different design approaches.

Overall, multiplier-less VLSI architectures demonstrate considerable potential for achieving high-speed and low-power 2-D DWT implementations. The study concludes that such techniques are highly suitable for real-time and resource-constrained applications, including embedded and portable image processing systems. Future research directions include the integration of advanced adder architectures and optimization techniques to further improve performance and scalability.