Review of Low Power Pulse Triggered Shift Register based on D-Flip Flops using MTCMOS Techniqu
Keywords:
SRAM, Dual Power Supply, Low PowerAbstract
A clock system consumes above 25% of the total system power. Flip-flops (FFs) are widely used as the basic storage element in all kinds of digital structures. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. Two important features are embedded in this flip-flop architecture. Firstly, the enhancement in width and height of trigger pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90 nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs.
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