High Speed and Area Efficient Matrix Multiplier based on Canonic Signed Digit Technique
Keywords:
Look Up Table (LUT), Read Only Memory (ROM), CSD Technique, Xilinx SimulationAbstract
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. Matrix multiplication is the kernel operation used in many transform, image and discrete signal processing application. We develop new algorithms and new techniques for matrix multiplication on configurable devices. In this paper, we have proposed designs for matrix-matrix multiplication. These design reduced hardware complexity, throughput rate and different input/output data format to match different application needs. In spite of complexity involved in canonic signed digit (CSD), its implementation is increasing day by day. Due to which high speed adder architecture become important. Several architecture designs have been developed to increase the efficiency of the multiplier-less technique. In this paper, we introduce an architecture that performs high speed matrix multiplier using CSD technique. These designs are implementation Xilinx Vertex device family.
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