COMPARATIVE DESIGNING OF POWER EFFICIENT AND HIGH-SPEED DOMINO LOGIC
Keywords:
Domino Circuit, Low Power, High Speed, CMOSAbstract
The microprocessors in the modern era are propelled by high speed, small area and low power circuits. Dynamic logic circuits are used for high performance and high speed applications. Wide OR gates are used in Dynamic RAMs, Static RAMs, high speed processors and other high speed circuits. In spite of their high performance, dynamic logic circuit has high noise and extensive leakage which has caused problems for the circuits. To overcome these problems Domino logic circuits are used which reduce sub threshold leakage current in standby mode and improve noise immunity for wide OR gates. High noise sensitivity is the result of sub threshold leakage current that flows through the evaluation network. With the advancements in CMOS manufacturing process to scale down into the ultra deep sub-micron regime, the leakage current becomes an increasingly. The conventional footed standard domino logic is modified to add a new circuit to improve leakage tolerance, especially in the initial phase of evaluation. The conditions for our simulations are: CMOS 90nm and 65nm technology, 1V and 0.9V power supply and bottleneck operating temperature of 27°C.
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