Optimization Result for 16-bit Discrete Hartley Transform using Partition Multiplier and 16-bit RCA with KSA Adder

Authors

  • Anil Kumar Yadav, Prof. Nishi Pandey , Prof. Abhishek Agwekar

Keywords:

Discrete Hartley Transform (DHT), Partition Multiplier, KSA, Number of Slice

Abstract

A discrete Hartley transform (DHT) algorithm can be efficiently implemented on a highly modular and parallel architecture having a regular structure is consisting of multiplier and adder. DHT is one of the transform used for converting data in time domain into frequency domain using only real values. We have proposed a new algorithm for calculating DHT of length 2^N, where N=3 and 4. We have implemented 16-bit DHT using partition multiplier and 16-bit ripple carry adder (RCA) with kogge stone adder (KSA). Partition multiplier based on KSA as an improvement in place of simple multiplication used in conventional DHT. This paper gives a comparison between conventional DHT algorithm and proposed DHT algorithm in terms of delays and area. It is also comparison of 16-bit conventional adder and proposed RCA with KSA adder in term of delay and area.

References

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How to Cite

Anil Kumar Yadav, Prof. Nishi Pandey , Prof. Abhishek Agwekar. (2022). Optimization Result for 16-bit Discrete Hartley Transform using Partition Multiplier and 16-bit RCA with KSA Adder. International Journal of Research & Technology, 10(3), 1–5. Retrieved from https://ijrt.org/j/article/view/288

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