Efficient VLSI Architecture for Modulo 2n+1 Multiplier using n-bit Inverted Adder
Keywords:
2-Stage Inverted n-Bit Adder, Modulo Multiplier, Residue Number System (RNS)Abstract
Efficient modulo 2n+12^n+12n+1 multipliers is proposed. According to our algorithm, the resulting partial products are reduced by an inverted and carry save adder to two operands, which are finally added by a 2-stage inverted n-bit adder. By using the 2-stage inverted n-bit adder, the new multipliers reduce the number of the partial product to n/2 for even and (n+1)/2 for odd except for one correction term. The analytical and experimental result indicates that the new modulo 2n+12^n+12n+1 multipliers offer enhanced operation among all the efficient existing solutions.
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