Review Paper of Binary Codes for Error Detection and Correction for FPGA Implementation
Keywords:
Golay Code, Decoder, Encoder, Field Programmable Gate Array (FPGA)Abstract
Golay Code is a type of Error Correction code discovered and performance very close to Shanon’s limit. Good error correcting performance enables reliable communication. Since its discovery by Marcel J.E. Golay there is more research going on for its efficient construction and implementation. The binary Golay code (G23) is represented as (23, 12, 7), while the extended binary Golay code (G24) is as (24, 12, 8). High speed with low-latency architecture has been designed and implemented in Virtex-4 FPGA for Golay encoder without incorporating linear feedback shift register. This brief also presents an optimized and low-complexity decoding architecture for extended binary Golay code (24, 12, 8) based on an incomplete maximum likelihood decoding scheme.
References
Shivani Tambatkar, Siddharth Narayana Menon, Sudarshan. V, M. Vinothini and N. S. Murty, “Error Detection and Correction in Semiconductor Memories using 3D Parity Check code with Hamming Code”, International Conference on Communication and Signal Processing, April 6-8, IEEE 2017, India.
Pallavi Bhoyar, “Design of Encoder and Decoder for Golay Code”, International Conference on Communication and Signal Processing, April 6-8, IEEE 2016, India.
Pedro Reviriego, Shanshan Liu, Lily Xiao, and Juan Antonio Maestro, “An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 34, No. 3, pp. 01-04, 2016.
Satyabrata SaranagI and Swapna Banerjee, “Efficient Hardware Implementation of Encoder and Decoder for the Golay Code”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2014.
P. Adebe, D. G. Toro, and C. Jego, “Design of an efficient maximum likelihood soft decoder for systematic short block codes,” IEEE Trans. Signal Process. vol. 60, no. 7, pp. 3914–3919, July 2012.
T.-C. Liu, H.-C. Chang, H.-P. Lee, and T.-K. Truong, “On the decoding of the (24, 12, 8) Golay Code,” Inf. Sci., vol. 180, no. 13, pp. 4729–4736, Dec. 2010.
M.-H. Hue, Y.-C. Su, J.-H. Chen, Z.-H. Chen, and Y. Chang, “High-speed low-complexity Golay decoder based on syndrome-oriented demodulation,” in Proc. Int. Conf. Inf. Commun. Signal Process. (ICICS), Dec. 2009, pp. 1–4.
Ayomyto B. Abasadead and Craig E. Hughes, Senior Member, IEEE, “VLSI Implementation of a Maximum-Likelihood Decoder for the Golay (24, 12) Code”, IEEE Journal on Selected Areas in Communications, VOL. 6, NO. 4, APRIL 1988.
B. Honary and G. Markarian, “New simple encoder and trellis decoder for Golay codes”, Electronics Letters 29th December 1993 Vol. 29 No. 25.
Xiao-Hong Peng, Member, IEEE, and Paddy G. Farrell, Life Fellow, IEEE, “High level parallel and SD soft-decision Golay Code Decoders with Application in Turbo Receiver Schemes”, IEEE Manuscript received January 19, 2005; revised April 13, 2005 and December15, 2005, IEEE Transaction.
Yuval Cassuto and Jinhong Yuan, “On the (24, 12, 8) Golay code with optimized permutetric decoding,” in Proc. IEEE Int. Symp. Inf. Theory (ISIT), Seattle, WA, USA, July 2006.
W. Guo, “A high-speed parallel hard and soft-decision Golay Decoder”, Proc. IEEE Int. Conf. Acoustics, Speech, Signal Process. (ICASSP), vol. 1, pp. 749–752, 2002.
Gregory Seroussi, Guiseppe Patane; and Marco Russo, “Parallel VLSI Architectures for the 24-Bit Systematic Golay Code”, IEEE Transactions On Computers, October 2003.
Downloads
How to Cite
Issue
Section
License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
