Design of 16 x 16 Multiplier Using Vedic Mathematics

Abstract

The need of low area and high speed Multiplier is increasing as the need of high speed processors are needed. Vedic arithmetic is that the traditional system of arithmetic which has a novel technique of calculations supported sixteen Sutras that are discovered by Sri Bharti Krishna Tirthaji. Any processor’s performance depends on 3 vital factors specifically speed, space and power. A higher trade-off between these factors makes the processor, a good one. Multipliers are the usually used architectures within the processor. If the performance of those multipliers is improved then powerful processors is created in future. During this work, the planned number style supported the sutra- ‘Urdhva Tiryakbhyam’ of Vedic arithmetic is analyzed and also the performance results of the number are compared with standard multipliers. Extremely economical arithmetic operations are necessary to appreciate the specified performance in several periods of time systems and digital image method applications. Altogether these applications, one of the necessary arithmetic operations of performed is to multiply and accumulate with a little method time (delay). The multipliers used in Square and cube architecture have to be more efficient in area and also in speed.