Implementation of High Speed 16 x 16 Multiplier Using Vedic Mathematics
Keywords:
Vedic multiplier, Array Multiplier, Vedic Mathematics, Urdhva-TiryagbhyamAbstract
The need of low area and high speed Multiplier is increasing as the need of high speed processors are needed. Vedic arithmetic is that the traditional system of arithmetic which has a novel technique of calculations supported sixteen Sutras that are discovered by Sri Bharti Krishna Tirthaji. Any processor’s performance depends on 3 vital factors specifically speed, space and power. In this paper a multiplier is implemented based on Nikhilam sutra with binary excess unit. The ripple carry adder in the multiplier architecture increases the speed of addition of partial products. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.
References
S.P. Poshakar, R.S. Sisal, K.M. Gaikwad, M.M. Patil, Rushikesh Borse “Design and Implementation of 16 x 16 Multiplier Using Vedic Mathematics” International Conference on Industrial Instrumentation and Control (ICIC)-College of Engineering Pune, India. May 28-30, 2015.
Sudeep M. C., Sharath Bimba, M. Mahendra Vucha, “Design and FPGA Implementation of High Speed Vedic Multiplier.” International Journal of Computer Applications, Volume 90–No. 16, March 2014.
G. Vadiviyanathan, K. Venkatesan, S. Sivaramakrishnan, S. Siva, and S. Jayakumar, “Simulation and Implementation of Vedic Multiplier Using VHDL Code.” International Journal of Scientific & Engineering Research, Volume 4, January 2013.
R. Sridevi, Anirudh Palakurthi, Akhila Sadhula, Hafsa Mahreen, “Design of High Speed Multiplier (Ancient Vedic Mathematics Approach).” International Journal of Engineering Research, Volume No. 2, pp. 183–186, July 2013.
Chilton Fernandes, Samarth Borkar, “Application of Vedic Mathematics in Computer Architecture.” International Journal of Advances in Engineering and Science (IJAES), Volume 1, September 2013.
Jagadguru Swami Sri Bharti Krishna Tirthaji Maharaja, “Vedic Mathematics or Sixteen Simple Mathematical Formulae from the Vedas,” Delhi (1965)°, Motilal Banarsidass, Varanasi, India.
C. Seshabhavi, K. Niranjan Kumar, “Design and Implementation of Vedic Multiplier.” International Journal of Computer Research and Development, Volume 8, pp. 23–28, September 2013.
Pramannanda B.S. Samarth, P. Sai Shashank, “Design and Implementation of 8-Bit Vedic Multiplier.” International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Volume 2, December 2013.
G. Ganesh Kumar, V. Charishma, “Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques.” International Journal of Scientific and Research Publications, Volume 2, Issue 3, March 2012.
Manoranjan Pradhan, Runupama Panda, Sashikan Kumar Sahu, “Modified Vedic Multiplier Architecture for High Speed Arithmetic Logic Unit.” International Journal of Computer Applications, Volume 21–No.6, May 2011.
R.S. Dhillon and A. Mlym, “A Digital Multiplier Architecture using Urdhva Tiryakbhyam Sutra of Vedic Mathematics.” IEEE Conference Proceedings, 2008.
Manjunath D. Chidgupkar, Mangesh T. Karad, “The Implementation of Vedic Algorithms in Digital Signal Processing.” Global J. of Eng. Educ., Vol. 8, No. 2.
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