VLSI Architecture for Discrete Cosine Transform using Reversible Logic for IOT

Abstract

In modern Internet of Things (IoT) applications, low-power and high-efficiency signal processing architectures are essential to enable real-time multimedia data compression, transmission, and analysis. The Discrete Cosine Transform (DCT) is a fundamental operation widely used in image and video compression standards such as JPEG and MPEG. However, conventional CMOS-based irreversible logic circuits consume significant power due to information loss during computation. To overcome this limitation, this paper presents a VLSI architecture for Discrete Cosine Transform using reversible logic, aimed at achieving ultra-low-power operation suitable for IoT edge devices. The proposed design employs reversible logic gates such as Feynman, Peres, Toffoli, and Fredkin to construct reversible adders and constant multipliers for DCT coefficient computation. This approach minimizes energy dissipation by preserving information and reducing the number of garbage outputs and ancilla inputs. The architecture is implemented for an 8-point DCT core using a multiplier-less structure optimized for area, delay, and power consumption. Simulation results demonstrate that the proposed reversible DCT design significantly reduces power dissipation and logic complexity compared to conventional DCT architectures. This makes it an effective solution for image and video processing in energy-constrained IoT systems, where energy efficiency and compact hardware design are critical performance parameters.