Low-Power Approximate Multiplier with Error Recovery using modified 4:2 and 7:3 Compressor
Keywords:
Vedic Multiplier, Compressor, Xilinx SimulationAbstract
Multiplication is an important function in arithmetic operations. A CPU (central processing unit) devotes a considerable amount of processing time in performing arithmetic operations. Multiplication requires substantially more hardware resources and processing time than addition and subtraction. Digital signal processors (DSPs) are the technology that is omnipresent in engineering Discipline. Fast multiplication is very important in DSPs for digital filter, convolution, Fourier transforms etc. In this proposed research work an attempt will make for making a novel multiplier using Nikhilam Sutra and Kogge stone adder. The proposed multiplier will have not only fast response but also having less number of component, area and power consumption.
References
Antonino Macaluso, Davide De Caro, Salvatore Perri, Nicola Petra and Gennaro Di Meo, “Low-Power Approximate Multiplier With Error Recovery Using a New Approximate 4-2 Compressor,” IEEE 2020.
Y. Guo, H. Sun, L. Guo, and S. Kimura, “Low-Cost Approximate Multipliers Design using Probability-Driven Inexact Compressors,” IEEE Asia Pacific Conf. Circuits Syst., pp. 289–294, 2018.
D. Esposito and S. Lee, “Multipliers with Approximate 4-2 Compressors and Error Recovery Modules,” IEEE Embed. Syst. Lett., vol. 10, no.1, pp. 6–9, 2018.
D. Esposito, A.G.M. Strollo, E. Napoli, D. De Caro, and N. Petra, “Approximate multipliers based on new approximate compressors,” IEEE Trans. Circuits Syst. I, vol. 65, no. 12, pp. 4169–4182, 2018.
M. S. Ansari, H. Jiang, B. F. Cockburn, and J. Han, “Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors,” IEEE J. Emerg. Sel. Top. Circuits Syst., vol. 8, no. 3, pp. 404–416, 2018.
J. Qiqieh, R. Shafik, G. Tarawneh, D. Sokolov, S. Das, and A. Yakovlev, “Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression.” in Proc. DATE Conference & Exhibition, 2017, pp. 7–12.
O. Akbari, M. Kamal, A. Afzali-Kusha, and M. Pedram, “Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers,” IEEE Trans. VLSI., vol. 25, no. 4, pp. 1352–1361, 2017.
D. Esposito, A.G.M. Strollo, and M. Alioto, “Low-power approximate MAC unit,” Proc. PRIME 2017 – 13th Conf. PhD Res. Microelectron. Electron. pp. 81–84, 2017.
W. El-Harouni et al., “Embracing approximate computing for energy efficient motion estimation in high efficiency video coding,” Proc. DATE Conference, 2017, Lausanne, 2017, pp. 1384–1389.
B. Moons and M. Verhelst, “An Energy-Efficient Precision-Scalable ConvNet Processor in 40 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 52, no. 4, pp. 904-914, April 2017.
G. Gokhale and P. D. Bhoirange, “Design of Vedic Multiplier using Area-Efficient Carry Select Adder,” 4th IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI-2015), Kochi, August 10-13, 2015, India.
G. Gokhale and N. S. R. Gokhale, “Design of Area and Delay Efficient Vedic Multiplier Using Carry Select Adder,” 4th IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI-2015), Kochi, August 10-13, 2015, India.
Pavan Kumar, Saiprasad Goud, and A Radhika had published their research with the title “FPGA Implementation of high speed 8-bit Vedic multiplier using barrel shifter”, 978-1-4673-6150-713 IEEE.
B. Madhu Latha1, B. Nageswar Rao, published their research with title “Design and Implementation of High Speed 8-Bit Vedic Multiplier on FPGA” International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 3, Issue 8, August 2014.
A Murali, G Vijaya Padma, T Saritha, published their research with title “An Optimized Implementation of Vedic Multiplier Using Barrel Shifter in FPGA Technology”, Journal of Innovative Engineering 2014, 2(2).
Sweeta Khatri, Ghanshyam Jangid, “FPGA Implementation of 64-bit fast multiplier using barrel shifter” Vol. 2 Issue VII, July 2014 ISSN: 2321-9653.
Jon J. Billore, D.R. Rotake, “FPGA implementation of high speed 8 Bit Vedic Multiplier using Fast adders” Journal of VLSI and Signal Processing, Volume 4, Issue 3, Ver. II (May-Jun. 2014), pp 54-59 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197.
S. R. Kerur, Prakash Narchi, Jayashree C. N, Harish M Kittur and Girish V. A, “Implementation of Vedic Multiplier for Digital Signal processing” International Conference on VLSI, Communication & Instrumentation (ICVCI) 2011.
Vaibhav Jindal, Mr. Navid Zafar Rizvi, Dinesh Kumar Singh “VHDL Code of Vedic Multiplierwith Minimum Delay Architecture” National Conference on Synergetic Trends in engineering and Technology (STET-2014) International Journal of Engineering and Technical Research ISSN: 2321-0869, Special Issue.
Bhavin D Marul, Afzal Davadiya “VHDL Implementation of 8-Bit Vedic Multiplier Using Barrel Shifter” International Journal for Scientific Research & Development Vol. 2, Issue 01, 2014 | ISSN (online): 2321-0613.
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