Review of Distributed Arithmetic based Discrete Wavelet Transform
Keywords:
1-D Discrete Wavelet Transform (DWT), Distributed Arithmetic (DA), Low Pass Filter, High Pass Filter, Xilinx SimulationAbstract
Conventional Distributed Arithmetic (DA) is widely used in Field Programmable Gate Array (FPGA) design due to its ability to achieve high speed and regularity through on-chip ROM. In this paper, we present a high-speed, area-efficient 1-D Discrete Wavelet Transform (DWT) using a 9/7 filter based on the DA technique. This architecture eliminates the need for ROM, multiplication, and subtraction, thereby improving area efficiency. Additionally, DA exposes the redundancy in the adder array, which contains only binary entries of 0 and 1. The proposed structure supports any image pixel value size and any level of decomposition, ensuring flexibility in image processing applications. The parallel structure achieves 100% hardware utilization efficiency, making it highly suitable for real-time and resource-constrained systems.
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