VLSI Architecture for Matrix Multiplier using Parallel To Parallel Input Multiple Output Technique
Keywords:
Matrix Multiplication, Parallel to Parallel Input Multiple Output (PPI-MO), Round based Approximated Multipliers (ROAM)Abstract
In the present scenario, the rapid growth of wireless communication, multimedia applications, robotics and graphics increases the demand for resource efficient, high throughput and low power digital signal processing (DSP) systems. Matrix multiplication (MM) is the most widely used fundamental processing element in almost all DSP systems ranging from audio/video signal processing to wireless sensor networks. Hardware implementation of MM requires a huge number of arithmetic operations that affect the speed and consumes more area and power. Pipelining and parallel processing are the two methods used in the DSP systems to reduce the area. MM is the kernel operation used in many transform, image and discrete signal processing application. We develop new algorithms and new techniques for MM on configurable devices. In this paper, we have proposed MM using round based approximated multipliers. This design reduced hardware complexity, delay and input/output data format to match different application needs. The PPI-MO based MM is design Xilinx software and simulated number of slice, look up table and delay.
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