Design of Capacitive DAC for a 14-bit Differential Successive Approximation Register ADC
Keywords:
SAR, ADC, DAC, VerilogAbstract
In this paper, Verilog-A based models of the comparator, SAR logic, switches, etc. of SAR ADC have been developed as ideal blocks to simulate in Cadence® Virtuoso® Analog Design Environment. Subsequently, 14-bit differential SAR ADC has been designed considering both conventional CDAC and optimally designed split CDAC integrating the Verilog-AMS based ideal blocks. Furthermore, a Verilog-AMS based testing module of INL (Integral non-linearity) and DNL (Differential non-linearity) for 14-bit differential SAR ADC using code is developed. Finally, INL and DNL have been calculated with developed code for a different resolution, and spectrum analysis of output signal has also been done.
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