VLSI Architecture for Radix-2 FFT using Bidirectional Gate based on Modified Carry Select Adder
Keywords:
Fast Fourier Transform (FFT), Modified Carry Select Adder (MCSLA), Delay, SliceAbstract
Fast Fourier Transform (FFT) is one of the most widely used signal processing algorithms in modern communication, image processing, biomedical systems, and wireless applications. The performance of FFT processors is primarily influenced by arithmetic units, particularly adders, which significantly affect the overall delay, power consumption, and hardware complexity. This paper presents a VLSI architecture for a Radix-2 FFT employing a Bidirectional Gate (BDG)-based Modified Carry Select Adder (MCSLA) to achieve high-speed and area-efficient computation. The proposed architecture replaces the conventional Carry Select Adder with an optimized MCSLA that utilizes bidirectional gate logic to minimize redundant hardware while maintaining fast carry propagation. The butterfly processing elements are redesigned using the proposed adder, resulting in reduced critical path delay and improved computational efficiency. The architecture is implemented and evaluated using standard VLSI design tools, and its performance is analyzed in terms of propagation delay, power consumption, silicon area, and Power-Delay Product (PDP). Experimental results demonstrate that the proposed BDG-MCSLA-based Radix-2 FFT architecture achieves lower delay, reduced hardware utilization, and improved energy efficiency compared with conventional CSLA-based FFT implementations. The proposed design is well suited for high-performance digital signal processing applications, including OFDM systems, software-defined radio, medical imaging, and real-time multimedia processing, where low power and high throughput are essential.
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