Different Types of Combinational Circuit based on Reversible Gate: A Systematic Review
Keywords:
Reversible Logic, Reversible Gates, Combinational Circuits, Quantum Computing, Low-Power VLSI Design, Feynman GateAbstract
Reversible logic has emerged as a promising paradigm in low-power digital system design due to its ability to minimize information loss and reduce energy dissipation. As conventional logic circuits face increasing challenges related to power consumption, heat generation, and scalability, reversible computing offers an efficient alternative for applications in VLSI design, quantum computing, nanotechnology, and optical information processing. Combinational circuits designed using reversible gates play a vital role in the development of energy-efficient digital systems. Various reversible gates such as Feynman Gate, Toffoli Gate, Fredkin Gate, Peres Gate, HNG Gate, and Double Feynman Gate have been extensively employed to realize combinational circuits including adders, subtractors, multiplexers, decoders, encoders, comparators, and arithmetic logic units.
This systematic review presents a comprehensive analysis of different types of combinational circuits based on reversible gates reported in recent literature. The review examines the design methodologies, performance parameters, and optimization techniques used in reversible combinational circuit design. Key evaluation metrics such as quantum cost, gate count, garbage outputs, constant inputs, propagation delay, and hardware complexity are discussed and compared across various implementations. Furthermore, the study highlights the advantages, limitations, and emerging trends in reversible logic-based combinational circuit design. The findings indicate that reversible gates significantly contribute to power-efficient computation and provide a strong foundation for future developments in quantum and next-generation computing systems. This review serves as a valuable reference for researchers and designers working in the fields of low-power VLSI design, reversible computing, and quantum technologies.
References
Kanchan S. Tiwari, “Design of generic vedic ALU using reversible logic”, Memories - Materials, Devices, Circuits and Systems 9, 100121, 2025.
S. Sen, P. Saha, and S. Saha, “FPGA-Supported HDL Approach to Implement Reversible Logic Gate-Based ALU,” Proc. IEEE 11th Int. Conf. on Internet of Everything, Microwave Engineering, Communication and Networks (IEMECON), pp. 1–5, 2023.
A. P. Sooriamala, A. K. Thomas, and R. Korah, “Design and Study of Circuits Using Reversible Logic,” Proc. 2nd Int. Conf. on Electronics and Sustainable Communication Systems (ICESC), pp. 213–217, 2021.
M. Swathi and B. Rudra, “Implementation of Reversible Logic Gates with Quantum Gates,” Proc. IEEE 11th Annu. Computing and Communication Workshop and Conference (CCWC), pp. 1557–1563, 2021.
Snigdha Chowdhury Kolay, Dr. Subrata Chattopadhyay and Mandakinee Bandyopadhyay, “Design and Development of SS Reversible Logic Gate and its Application as Adder & Subtractor”, Proceedings of the Fifth International Conference on Inventive Computation Technologies (ICICT-2020).
Dr. B. Balaji, M. Aditya, Dr. E. Radhamma, Dr.V. Reddy, Dr. Y. Naresh, “Full Adder/ Subtractor Using Reversible Logic,” International Journal of Pure and Applied Mathematics, vol. 120, pp. 437-446, 2018.
Batish, Kirti, Shruti Pathak, Raghav Gupta, “Comparative Analysis for Performance Evaluation of Full Adders Using Reversible Logic Gates,” 2018 International Conference on Intelligent Circuits and Systems, ICICS, pp. 126-132, 2018.
A. Gupta, P. Singla, J. Gupta, N. Maheshwari “An Improved Structure of Reversible Adder And Subtractor,” International Journal of Electronics and Computer Science Engineering, vol. 2, pp. 712-718, May 2017.
Gopi Chand Naguboina and K. Anusudha, “Design and Synthesis of Combinational Circuits Using Reversible Decoder in Xilinx”, IEEE International Conference on Computer, Communication, and Signal Processing (ICCCSP-2017).
Marcin Bryk, Kryszt Gracki, Pawal Kerntop and Marek Pawlowski, “Encryption using reconfigurable reversible logic gate and its simulation in FPGAs”, Mixed Design of Integrated Circuits and Systems, 2016 MIXDES - 23rd International Conference IEEE Xplore: 04 August 2016.
Umeshkumar, LavishaSahu, Uma Sharma, “Performance Evaluation of Reversible Logic Gates”, International Conference on ICT in Business Industry & Government (ICTBIG), IEEE 2016.
M. Aditya, Y. B. N. Kumar, M. H. Vasantha, "Reversible full/half adder with optimum power dissipation,” 10th International Conference on Intelligent Systems and Control (ISCO), pp. 1-4, 2016.
P. Gowthami, RVS Satyanarayana, “Design of Digital Adder Using Reversible Logic,” Gowthami P Int. Journal of Engineering Research and Applications, vol. 6, pp. 53- 57, February 2016.
R. Kumar, P. Ranjan, D. Das, “Moore’s Law,” International Journal of Modern Trends in Engineering and Research, vol. 3, pp. 508-514, April 2016.
M. Haghparast and A. Bolhassani Optimized parity preserving quantum reversible full adder/subtractor. International Journal of Quantum Information vol. 14 no. 3 2016.
Downloads
How to Cite
Issue
Section
License

This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.




