Review Paper of Binary Codes for Error Detection and Correction

Authors

  • Shrishti Singh, Prof. Ravi Bhushan Roy

Keywords:

Golay Code, Decoder, Encoder, Field Programmable Gate Array (FPGA)

Abstract

Golay Code is a type of Error Correction code discovered and performance very close to Shanon’s limit. Good error correcting performance enables reliable communication. Since its discovery by Marcel J.E. Golay there is more research going on for its efficient construction and implementation. The binary Golay code (G23) is represented as (23, 12, 7), while the extended binary Golay code (G24) is as (24, 12, 8). High speed with low-latency architecture has been designed and implemented in Virtex-4 FPGA for Golay encoder without incorporating linear feedback shift register. This brief also presents an optimized and low-complexity decoding architecture for extended binary Golay code (24, 12, 8) based on an incomplete maximum likelihood decoding scheme.

 

References

Shivani Tambatkar, Siddharth Narayana Menon, Sudarshan. V, M. Vinodhini and N. S. Murty, “Error Detection and Correction in Semiconductor Memories using 3D Parity Check Code with Hamming Code”, International Conference on Communication and Signal Processing, April 6-8, 2017, India.

Pallavi Bhoyar, “Design of Encoder and Decoder for Golay code”, International Conference on Communication and Signal Processing, April 6-8, IEEE 2016, India.

Pedro Reviriego, Shanshan Liu, Liyi Xiao, and Juan Antonio Maestro, “An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code”, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 34, No. 3, pp. 01-04, 2016.

Satyabrata Sarangi and Swapna Banerjee, “Efficient Hardware Implementation of Encoder and Decoder for Golay Code”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2014.

P. Adde, D. G. Toro, and C. Jego, “Design of an efficient maximum likelihood soft decoder for systematic short block codes,” IEEE Trans. Signal Process. vol. 60, no. 7, pp. 3914–3919, Jul. 2012.

T.-C. Lin, H.-C. Chang, H.-P. Lee, and T.-K. Truong, “On the decoding of the (24, 12, 8) Golay Code,” Inf. Sci., vol. 180, no. 23, pp. 4729–4736, Dec. 2010.

M.-H. Jing, Y.-C. Su, J.-H. Chen, Z.-H. Chen, and Y. Chang,“High-speed low-complexity Golay decoder based on syndromeweight determination,” in Proc. 7th Int. Conf. Inf., Commun., Signal Process. (ICICS), Dec. 2009, pp. 1–4.

Ayyoob D. Abbaszadeh and Craig K. Rushforth, Senior Member, IEEE, “VLSI Implementation of a Maximum-Likelihood Decoder for the Golay (24, 12) Code”, IEEE Journal on Selected Areas in Communications. VOL. 6, NO. 3, APRIL 1988.

B. Honary and G. Markarian, “New simple encoder and trellis decoder for Golay codes”, Electronics Letters 9th December 1993 Vol. 29 No. 25.

Xiao-Hong Peng, Member, IEEE, and Paddy G. Farrell, Life Fellow, IEEE, “On Construction of the (24, 12, 8) Golay Codes”, IEEE Manuscript received January 19, 2005; revised July 7, 2005 and December15, 2005, respectively.

W. Cao, “High-speed parallel VLSI-architecture for the (24, 12) Golay decoder with optimized permutation decoding,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Connecting World, vol. 4. May 1996, pp. 61–64.

W. Cao, “High-speed parallel hard and soft-decision Golay decoder: Algorithm and VLSI-architecture,” in Proc. IEEE Int. Conf. Acoust., Speech, Signal Process. (ICASSP)., vol. 6. May 1996, pp. 3295–3297.

Giuseppe Campobello, Giuseppe Patane`, and Marco Russo, “Parallel CRC Realization”, IEEE Transactions On Computers, Vol. 52, No. 10, October 2003.

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How to Cite

Shrishti Singh, Prof. Ravi Bhushan Roy. (2019). Review Paper of Binary Codes for Error Detection and Correction . International Journal of Research & Technology, 7(4), 1–5. Retrieved from https://ijrt.org/j/article/view/103