High Speed and Area Efficient Adjoint Matrix using Booth Multiplier for FPGA Implementation
Keywords:
IEEE754, Single Precision Floating Point (SP FP), Double Precision Floating Point (DP FP), Matrix MultiplicationAbstract
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. Matrix multiplication is the kernel operation used in many transform, image and discrete signal processing application. We develop new algorithms and new techniques for matrix multiplication on configurable devices. In this paper, we have proposed three designs for matrix-matrix multiplication. These design reduced hardware complexity, throughput rate and different input/output data format to match different application needs. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Due to which high speed adder architecture become important. Several adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed IEEE 754 floating point multiplier using carry select adder (CSA). Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family.
References
Di Yan, Wei-Xing Wang, Lei Luo, Member, IEEE and Xiao-Wei Zhang, “Revisiting the Adjoint Matrix for FPGA Calculating the Triangular Matrix Inversion”, IEEE Transactions on Circuits and Systems II: Express Briefs, 2020.
X.-W. Zhang, L. Zuo, M. Li and J.-X. Guo, “High-throughput FPGA implementation of Matrix inversion for control systems,” Accepted by IEEE Trans. Ind. Electron., 2020.
C. Zhang, et al., “On the low-complexity, hardware-friendly tridiagonal matrix inversion for correlated massive MIMO systems,” IEEE Trans. Vehic. Tech., vol. 68, no. 7, pp. 6272-6285, Jul. 2019.
Y.-W. Xu, Y. Xi, J. Lan and T.-F. Jiang, “An improved predictive controller on the FPGA by hardware matrix inversion,” IEEE Trans. Ind. Electron., vol. 65, no. 9, pp. 7395–7405, Sep. 2018.
Lakshmi kiran Mukkara and K.Venkata Ramanaiah, “A Simple Novel Floating Point Matrix Multiplier VLSI Architecture for Digital Image Compression Applications”, 2nd International Conference on Inventive Communication and Computational Technologies (ICICCT 2018).
Soumya Havaldar, K S Gurumurthy, “Design of Vedic IEEE 754 Floating Point Multiplier”, IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India.
Ragini Parte and Jitendra Jain, “Analysis of Effects of using Exponent Adders in IEEE - 754 Multiplier by VHDL”, 2015 International Conference on Circuit, Power and Computing Technologies [ICCPCT] 978-1-4799-7074-2/15/$31.00 ©2015 IEEE.
Ross Thompson and James E. Stine, “An IEEE 754 Double-Precision Floating-Point Multiplier for Denormalized and Normalized Floating-Point Numbers”, International conference on IEEE 2015.
M. K. Jaiswal and R. C. C. Cheung, “High Performance FPGA Implementation of Double Precision Floating Point Adder/Subtractor”, in International Journal of Hybrid Information Technology, vol. 4, no. 4, (2011) October.
B. Fagin and C. Renard, "Field Programmable Gate Arrays and Floating Point Arithmetic," IEEE Transactions on VLSI, vol. 2, no. 3, pp. 365-367, 1994.
N. Shirazi, A. Walters, and P. Athanas, "Quantitative Analysis of Floating Point Arithmetic on FPGA Based Custom Computing Machines," Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM’95), pp.155-162, 1995.
Malik and S.-B. Ko, “A Study on the Floating-Point Adder in FPGAs”, in Canadian Conference on Electrical and Computer Engineering (CCECE-06), (2006) May, pp. 86–89.
D. Sangwan and M. K. Yadav, “Design and Implementation of Adder/Subtractor and Multiplication Units for Floating-Point Arithmetic”, in International Journal of Electronics Engineering, (2010), pp. 197-203.
L. Louca, T. A. Cook and W. H. Johnson, “Implementation of IEEE Single Precision Floating Point Addition and Multiplication on FPGAs”, Proceedings of 83rd IEEE Symposium on FPGAs for Custom Computing Machines (FCCM’96), (1996), pp. 107–116.
Jaenicke and W. Luk, "Parameterizied Floating-Point Arithmetic on FPGAs", Proc. of IEEE ICASSP, vol. 2, (2001), pp. 897-900.
Lee and N. Burgess, “Parameterisable Floating-Point Operations on FPGA”, Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems, and Computers, (2002).
M. Al-Ashrafy, A. Salem, W. Anis, “An Efficient Implementation of Floating Point Multiplier”, Saudi International Electronics, Communications and Photonics Conference (SIECPC), (2011) April 24-26, pp. 1-5.
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