Review Paper on High Speed Error Recovery Multiplier using Compressor based Adder
Keywords:
Compressor, Compressor Based Adder, XOR-XNOR Gate, Different InputAbstract
he ever growing demand for portable applications like mobile phones and laptops under explosive proportions has made the designers to strive for smaller silicon area, high speed, longer battery life and more reliability. XOR/XNOR gates are the basic building blocks of various digital system applications like adders, multipliers, comparators, ALUs, MAC units, parity generators/checkers and error detection and correction coders etc. In this paper, the studied of different XOR/XNOR logic circuits for two input, three input, multi input, differential outputs, self-checking operation, low voltage working and ternary logic is present.
The studied of two input, three input and multi input circuits are simple and symmetric which used the topology of pass transistor logic and transmission gate logic. All the designs will simulate Xilinx software.
References
N. Hamed S. Timarchi "Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates" IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2018.
Low Power Approximate Adders for General Computing Using Differential Transmission Gate" on 28.03.2018 National Conference on Innovations in Communication and Computing NCICC’ 18 SNS College of Technology.
Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram, “Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 34, Issue 7, 2017.
M. A. Valashani S. Mirzakuchaki "A novel fast low-power and high-performance XOR-XNOR cell" Proc. IEEE Int. Symp. Circuits Syst. (ISCAS) vol. 1 pp. 694-697 May 2016.
P. Bhattacharyya et al. "Performance analysis of a low-power high speed hybrid 1-bit full adder circuit" IEEE Trans. Very Large Scale Integr. (VLSI) Syst. vol. 23 no. 10 pp. 2001-2008 Oct. 2015.
Josmin Thomas, R. Pushpangadan and Jinesh, “Comparative Study of Performance Vedic Multiplier on The Basis of Adders Used”, International Conference on Electrical and Computer Engineering, pp. 01-05, 2015 IEEE.
Abdoreza Pishvaie, Ghassem Jaberipur and Ali Jahanian, “Compressor CMOS (4:2) rceons pour less multiplication binary number”, Can. Journal Electronics Computation Engineering, Vol. 36, No. 3, summer 2013.
Rupa Kannan, Saiprasad Goud and A. Radhika, “FPGA Implementation of high speed 8-bit Vedic multiplier using barrel shifter”, International Conference on Digital Circuit and System, 2013 IEEE.
Abdoreza Pishvaie Ghassem Jaberipur Ali Jahanian “Improved CMOS (4:2) compressor design for parallel multipliers” Journal of Computers and Electrical Engineering pp. 1703-1716 Sep. 2012.
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