Design & Simulation of Second Stage & Three Stage OP-AMP Using 0.35µ µµ µm CMOS Technology
Keywords:
CMOS Analog Circuit, Second Stage CMOS Opera tional amplifier, Stability, Device Design, Scaling, Differential Amp, Three stage CMOS Operational amplifierAbstract
A method is presented in this paper for the design of high speed CMOS Operational Amplifiers (Op-Amp).This paper is to design a Second Stage and Three Stage CMOS Operational amplifier and analyze the results of various aspect ratios on the characteristics of this Op-Amp, which operates at 3V to 5V power supply using TSMC 0.35µm CMOS technology. They have acceptable resolution and high speed of operation and can be placed in relatively small area. The design is implemented in 0.18u M CMOS process. The design includes folded cascade op-amp with a unity gain frequency of 200MHz at 88° °° ° deg. The complete design topology of high gain-high bandwidth Op-Amp is presented between all characteristics such as Gain, Phase margin, CMRR etc. It also comprehensive improvements are seen in case of CMRR, PSRR, Offset Voltage and Transient performance at the expense of power and output resistance. Besides, for low power-low bandwidth application an optimum noise performance is achieved in this design. A Second stage Op-Amp the DC gain of the amplifier is 70 dB. The unity gain frequency and phase margin of the amplifier are 65 GHz and 43° and total power consumption of the Op-Amp is 0.070 mw. A Three stage OP-AMP the DC gain of the amplifier is 69 dB. The unity gain frequency and phase margin of the amplifier are 74 GHz and 43.5° and total power consumption of the Op Amp is 0.062 mw. for a parallel combination of 2 pF and 1 kΩ load. I used AWR (microwave office) software for implement this work
References
Appenzeller, J., Lin, Y., Knoch, J., Chen, Z., & Avouris, P. (2007). 1/f Noise in Carbon Nanotube Devices—On the Impact of Contact and Device Geometry. IEEE Transactions on Nanotechnology, 6(3), 368–373.
Marulanda, J. M., & Srivastava, A. (2007). Carrier Density and Effective Mass Calculations for Carbon Nanotubes. In ICICTD ’07 IEEE, pp. 1–4.
Nayebi, M., & Wooley, B. A. (1989). A 10-bit video BiCMOS track-and-hold amplifier. IEEE J. Solid-State Circuits, 24, 1507–1516.
Lim, P. J., & Wooley, B. A. (1991). A high speed sample and hold technique using a Miller hold capacitance. IEEE J. Solid-State Circuits, 26(4), 643–651.
Temes, G. C., Huang, Y., & Ferguson Jr., P. F. (1995). A high-frequency track and hold stage with offset and gain compensation. IEEE Trans. Circuits Syst. II, 42(8), 559–560.
Brigati, S., Maloberti, F., & Torelli, G. (1996). A CMOS sample and hold for high-speed ADCs. In Proc. IEEE Int. Symp. Circuits and Systems Circuits and Systems Connecting the World, 1, 163–166.
Shieh, J. H., Patil, M., & Sheu, B. J. (1986). Measurement and analysis of charge injection in MOS switches. IEEE J. Solid State Circuits, SC-22(2), 277–281.
Wegmann, G., Vittoz, E. A., & Rahali, F. (1987). Charge injection in analog MOS switches. IEEE J. Solid-State Circuits, SC-22(6), 1091–1097.
Xu, G., & Embabi, S. (2000). A systematic approach in constructing fully differential amplifiers. IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, 47(11), 1343–1347.
Shen, M., Hung, L., & Huang, P. (2006). A 1.2 V fully differential amplifier with buffered reverse nested Miller and feedforward compensations. In IEEE Asian Solid-State Circuits Conf (A-SSCC), pp. 171–174.
Pavan, S., Krishnapura, N., Pandarinathan, R., & Sankar, P. (2008). A power optimized continuous time ADC for audio applications. IEEE J. Solid-State Circuits, 43(2), 351–360.
Peng, X., & Sansen, W. (2005). Transconductance with capacitances feedback compensation for multistage amplifiers. IEEE J. Solid-State Circuits, 40(7), 1514–1520.
Saxena, V., & Baker, R. (2009). Indirect compensation techniques for three-stage CMOS Op-Amps. In 52nd IEEE Int. Midwest Symp. Circuits and Systems (MWSCAS), pp. 9–12.
Younis, A., & Hassoun, M. (2000). A High Speed Fully Differential CMOS Opamp. Proceedings of the IEEE Midwest Symposium on Circuits and Systems, 2, 780–783.
Allen, P. E., & Holberg, D. R. (2002). CMOS Analog Circuit Design. Oxford University Press.
Baker, R. J., Li, H. W., & Boyce, D. E. (1998). CMOS Circuit Design, Layout, and Simulation. IEEE Press.
Johns, D., & Martin, K. (1997). Analog Integrated Circuit Design. John Wiley & Sons.
Razavi, B. (2001). Design of Analog CMOS Integrated Circuits. McGraw-Hill.
TSMC. (2003). 0.18-Micron Technology. Taiwan Semiconductor Manufacturing Company Ltd., Taiwan, April.
Trontelj, L., Trontelj, J., Slivnik, T., Sosic, R., & Strle, D. (1987). Analog silicon compiler for switched capacitor filters. In Proc. IEEE Int. Conf. Computer-Aided Design, pp. 506–509.
Laarhoven, P. J. M. van, & Aarts, E. H. L. (1987). Simulated Annealing: Theory and Applications. Amsterdam, The Netherlands: Reidel.
Vandenberghe, L., Boyd, S., & El Gamal, A. (1997). Optimal wire and transistor sizing for circuits with non-tree topology. In Proc. 1997 IEEE/ACM Int. Conf. Computer Aided Design, pp. 252–259.
Vandenberghe, L., Boyd, S., & El Gamal, A. (1998). Optimizing dominant time constant in RC circuits. IEEE Trans. Computer-Aided Design, 17(2), 110–125.
Vanderbei, R. J. (1997). Linear Programming: Foundations and Extensions. Norwell, MA: Academic.
Wang, F., & Harjani, R. (1996). Optimal design of op amps for oversampled converters. In Proc. IEEE Custom Integrated Circuit Conf., pp. 15.5.1–15.5.4.
Downloads
How to Cite
Issue
Section
License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.