New Design of CMOS Current Comparator with reduced Delay Time and Marginal Power Consumption
Keywords:
Current Comparator, High Speed, PowerAbstract
This work proposes a new CMOS comparator with marginally low power consumption and reduced delay time, suitable for precision biasing of op-amps with acceptable power consumption and improved speed. The proposed circuit was simulated in a proprietary 180 nm CMOS process, using Cadence Spectre Simulator and models. The current comparator circuit demonstrated current pulses ranging from micro-amperes to nano-amperes, and its delay time and power consumption were measured after simulation. By incorporating the effect of different capacitances of the CMOS, the transient response confirms the reduced delay time, indicating high speed operation of the proposed comparator circuit. Additionally, the proposed comparator circuit consumes minimal power.
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