FPGA Implementation of Digital IF Filter with Low Complexity and Less Delay using Multi-rate Approach
Keywords:
Filter Coefficient, Digital IF Filter, Pass-band Multi-rate Approach.Abstract
Because of restricted recurrence assets, new administrations are being applied to the current frequencies, and specialist co-ops are apportioning a portion of the current frequencies for recently improved versatile interchanges. In light of this recurrence condition, repeater and base station frameworks for portable correspondences are getting more confused, and recurrence obstruction brought about by numerous groups and administrations is deteriorating. In this manner, a heterodyne recipient utilizing IF channels with high selectivity has been utilized to limit the obstruction between frequencies. Notwithstanding, repeater and base station frameworks in portable interchanges utilizing fixed IF channels can't effectively adapt to the use of different recurrence groups, the use of different administrations, and recurrence reusing. In this paper design digital IF filter using multi-rate approach. Multi-rate approach is reduced the hardware complexity is reduce in the way of adder and multiplier. Digital IF is implemented Xilinx software and simulate different parameter i.e. slice, LUTs, minimum frequency and delay.
References
Hyoeon Park, Myoungseok Yu, Yunho Jung, and Seongjoe Lee, “Design of Reconfigurable Digital IF Filter with Low Complexity”, IEEE Transactions on Circuits and Systems II, 2018.
Dwipayan Ray, Nithin V. George, and Pramod Kumar Meher, “Efficient Shift-Add Implementation of FIR Filters Using Variable Partition Hybrid Form Structures”, IEEE Transactions on Circuits And Systems—I: Regular Papers, Vol. 32, Issue 6, June 2018.
Mohamed Alawad and Mingjie Lin, “Memory-Efficient Probabilistic 2-D Finite Impulse Response (FIR) Filter”, IEEE Communication Letters, Vol. 99, No. 04, April 2017.
A. Mehmia, M. Dai, A. N. Willison, “Efficient half band FIR filter structures for RF and IF data converters”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 1 (2016): 64-68.
S. Dhabu, and A. P. Vinod, “Design and FPGA Implementation of Reconfigurable Linear-Phase Digital Filter With Wide Cutoff Frequency Range and Narrow Transition Bandwidth”, IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 63, no. 2, pp. 181-185, 2016.
Basant Kumar Mohanty and Pramod Kumar Meher, “High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 78, No. 06, April 2016.
Indranil Naitai, Indrajit Chakrabarti, and Swapna Banerjee, “An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multi-standard DUC”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014.
Sang Yoon Park and Pramod Kumar Meher, “Efficient FPGA and ASIC Realizations of DA-Based Reconfigurable FIR Digital Filter”, IEEE Transactions on Circuits And Systems-II: Express Briefs, 2014.
Pramod Kumar Meher, Shrutisagar Chandrasekaran, and Abbes Amira, “Distributed Arithmetic for FIR Filter Implementation on FPGA”, Proceedings of IC-BNMT, 2011.
Ms. S. Manjuli, Mr. V. Sornagopae, “An Efficient SQRT Architecture of Carry Select Adder Design by Common Boolean Logic”, 978-1-4673-5301-4/13/$31.00 ©2013 IEEE.
Basant K. Mohanty and Pramod Kumar Meher, “A High-Performance Energy-Efficient Architecture For FIR Adaptive Filter Based On New Distributed Arithmetic Formulation Of Block LMS Algorithm”, IEEE Transactions on Signal Processing, Vol. 61, No. 4, pp. 45-52, February 2013.
Downloads
How to Cite
Issue
Section
License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
