Survey Paper of Binary Arithmetic Codes for Error Detection and Correction
Keywords:
Error Detection, Error Correction, Binary Arithmetic CodesAbstract
In digital systems, the analog signals will change into digital sequence (in the form of bits). This sequence of bits is called as “Data stream”. The change in position of single bit also leads to catastrophic (major) error in data output. Almost in all electronic devices, we find errors and we use error detection and correction techniques to get the exact or approximate output. Error detection and correction codes based on redundant residue number systems are powerful tools to control and correct arithmetic processing and data transmission errors. Decoding the magnitude and location of a multiple error is a complex computational problem: it requires verifying a huge number of different possible combinations of erroneous residual digit positions in the error localization stage.
References
Kristjane Koleci, Paolo Santini, Marco Baldi, Franco Chiaraluce, Maurizio Martina And Guido Masera, “Efficient Hardware Implementation of the LEDAcrypt Decoder”, IEEE Access 2021.
P. Santini, M. Battaglioni, M. Baldi, and F. Chiaraluce, “Analysis of the error correction capability of LDPC and MDPC codes under parallel bit-flipping decoding and application to cryptography”, IEEE Trans. Communication, vol. 68, no. 8, pp. 4648–4660, Aug. 2020.
J. Hu, M. Baldi, P. Santini, N. Zeng, S. Ling, and H. Wang, “Lightweight key encapsulation using LDPC codes on FPGAs”, IEEE Trans. Comput., vol. 69, no. 3, pp. 327–341, Mar. 2020.
D. Zoni, A. Galimberti, and W. Fornaciari, “Efficient and scalable FPGA oriented design of QC-LDPC bit-flipping decoders for post-quantum cryptography”, IEEE Access, vol. 8, pp. 163419–163433, 2020.
K. Koleci, M. Baldi, M. Martina, and G. Masera, “Hardware implementation for code-based post-quantum asymmetric cryptography”, in Proc. 3rd Italian Conf. Cybersecurity (ITASEC), vol. 2597, Ancona, Italy, Feb. 2020, pp. 141–152.
D. Zoni, A. Galimberti, and W. Fornaciari, “Flexible and scalable FPGA oriented design of multipliers for large binary polynomials”, IEEE Access, vol. 8, pp. 75809–75821, 2020.
M. Baldi, A. Barenghi, F. Chiaraluce, G. Pelosi, and P. Santini, “LEDAcrypt: QC-LDPC code-based cryptosystems with bounded decryption failure rate”, in Code-Based Cryptography, M. Baldi, E. Persichetti, and P. Santini, Eds. Cham, Switzerland: Springer, 2019, pp. 11–43.
Shivani Tambatkar, Siddharth Narayana Menon, Sudarshan. V, M. Vinodhini and N. S. Murty, “Error Detection and Correction in Semiconductor Memories using 3D Parity Check Code with Hamming Code”, International Conference on Communication and Signal Processing, April 6–8, 2017, India.
Wenle Jin, Shaohua Wu, Erpeng Yang and Jian Jiao, “LDPC Convolutional Codes Coded Cooperation Based on Puncturing”, ISBN 978-89-968650-9-4 ICACCT2017 February 19–22, IEEE 2017.
Pallavi Bhoyar, “Design of Encoder and Decoder for Golay code”, International Conference on Communication and Signal Processing, April 6–8, IEEE 2017, India.
Manikandan J, Shruthi S, Mangala SJ and Agarwal VK, “Design and Implementation of Reconfigurable Coders for Communication Systems”, International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA), IEEE 2016.
Sindhujaa Muppalla and Koteswara Rao Vaddempudi, “A Novel VHDL Implementation of UART with Single Error Correction and Double Error Detection Capability”, SPACES-2015, Dept. of ECE, KL University.
Satyabrata Sarangi and Swapna Banerjee, “Efficient Hardware Implementation of Encoder and Decoder for Golay Code”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2014.
Nitin Patel, Naresh Patel, “VHDL Implementation of UART with BIST capability”, IEEE 4th ICCCNT, July 4–6, 2013, Tiruchengode, India.
Shumit Saha, Md. Ashikur Rahman, Amit Thakur, “Design and Implementation of a BIST Embedded High Speed RS-422 Utilized UART over FPGA”, IEEE 4th ICCCNT, July 4–6, 2013, Tiruchengode, India.
Downloads
How to Cite
Issue
Section
License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
