Low Power and Radiation Tolerance System on Chip (Soc) Architecture

Abstract

The design and assessment of a low-power, radiation-tolerant System-on-Chip (SoC) architecture appropriate for RTL-level VLSI implementation was the main goal of the current work. Instruction memory, ECC-protected data memory, a memory-mapped interface, UART, GPIO, timer, interrupt controller, watchdog timer, Power Management Unit (PMU), and Fault-Tolerance Controller (FTC) were all incorporated into a small 32-bit RV32I-compatible processing subsystem. Practical methods for FPGA-oriented RTL design featured peripheral sleep modes, operand isolation, synchronous clock-enable control, memory-enable management, and a decrease in pointless bus activity. Instead of using full-chip redundancy, radiation tolerance was added selectively. The provided dataset showed a 14.6% drop in dynamic power from 82.4 mW to 70.4 mW and a 9.1% decrease in overall power from 101.0 mW to 91.8 mW. LUT use rose from 4,920 to 6,835 and flip-flop usage from 3,280 to 4,725. The claimed maximum operational frequency dropped from 109.9 MHz for the baseline to 103.6 MHz, while the combined design remained above the selected 100 MHz threshold. There were 1,800 injected events in the specified RTL fault-injection campaign; 1,786 events were detected and 1,207 events were categorised as effectively mitigated, representing 99.2% detection and 67.1% successful mitigation.