Review on Development Process & characteristic analysis of SOI MOSFET devices
Keywords:
SOI, MOSFET, CMOS, wafer, Silicon, InsulatorAbstract
As the device count in an IC is running into billions per chip, the issue of power dissipation in the chip is becoming too critical. Due to decreasing device dimension the performance of the bulk Si MOSFET is limited by its fundamental physical limits such as reduction in carrier mobility due to impurities, increasing gate tunnelling effect as the gate oxide thickness decreases and increasing p-n junction leakage current as the junction become more and more shallow. These requirements have led to development of alternating technology. SOI (silicon on insulator) technology is one such alternative which can offer the performance as may be expected from the next generation technology. SOI technology offers significant advantages in design, fabrication and performance for many semiconductor circuits such as excellent isolation, improved latch up free operation, radiation hardness, reduced short channel effects, improved switching speeds and reduced leakage current, due to reduction in the drain-body capacitance. The reduction in the parasitic capacitances leads to improved switching speed and superior performance. This paper is focused on the brief of SOI MOSFET Technology, its characteristics, advantages and disadvantages of it.
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