A Comprehensive Review of Machine Learning Based Power Estimation Techniques for CMOS VLSI Circuits
Keywords:
CMOS VLSI, Power Estimation, Machine Learning, Low-Power Design, Feature Extraction, Deep Learning, CAD ToolsAbstract
Due to the advances in technology scaling, the increase in density in transistors, and the growing demand for energy-efficient systems in electronics, it is now impossible to ignore power consumption as a critical design constraint in modern CMOS VLSI circuits. An effective power estimation significantly influences performance, yield, and thermal stability across all the stages of the VLSI design. Traditional power estimation methods like SPICE-level simulation and various analytically derived or statistically inferred models yield a high level of accuracy but are impeded by elevated costs, long runtimes, and limited scalability, meaning they are simply unfit for early-stage design and quick design space exploration. In that regard, ML-based power estimation has started gaining significant interest since the last few years.This review paper gives an in-depth radio of machine learning techniques applied to power estimation in CMOS VLSI circuits. It looks at methodically regression-based models, tree-based ensemble methods, artificial neural networks, and state-of-the-art deep learning methods like convolutional, recurrent, and transformer architectures. It deals with the feature extraction methods that are most regularly used at the RTL, gate, and post-layout levels, at the same time as arguing that machine learning is good at catching the complex non-linear relations between the switching activity, structure parameters, and technology-dependent effects. In the paper, we argue that the ML-based techniques have edge in terms of speed, scalability, and adaptability compared to the traditional approaches.
References
Y. Zhang, X. Liu, and M. Chen, “Post-Synthesis Power Estimation of CMOS Circuits Using Random Forest Models,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 11, pp. 2215–2226, 2021.
R. Kumar and P. Singh, “RTL-Level Power Estimation Using Support Vector Regression for CMOS VLSI Designs,” IEEE Access, vol. 9, pp. 138421–138432, 2021.
H. Li, J. Wang, and Y. Sun, “Gate-Level Power Estimation Using Graph Neural Networks,” in Proc. Design Automation Conference (DAC), 2022, pp. 1–6.
S. Ahmed, T. Rahman, and M. Hasan, “Tree-Based Ensemble Learning for Accurate Power Modeling of VLSI Circuits,” Integration, the VLSI Journal, vol. 79, pp. 1–10, 2022.
J. Park, H. Lee, and S. Kim, “Hierarchical Power Estimation Using Deep Neural Networks,” Microelectronics Journal, vol. 134, pp. 105412, 2023.
X. Huang, Z. Li, and Y. Sun, “XGBoost-Based Power Estimation for Large-Scale CMOS Designs,” IEEE Access, vol. 11, pp. 21456–21467, 2023.
T. Wang, L. Zhou, and K. Qian, “CNN-Based Structural Feature Learning for Power Estimation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, no. 4, pp. 987–998, 2024.
M. Poid, A. Rossi, and F. Conti, “CENET-Based Neural Power Modeling for Hierarchical CMOS Designs,” Integration, the VLSI Journal, vol. 88, pp. 58–68, 2024.
X. Chen, Y. Li, and R. Gupta, “Transformer-Based Netlist Representation for Accurate Power Prediction,” in Proc. Design Automation Conference (DAC), 2025, pp. 1–6.
D. Patel and N. Mehta, “Lightweight Machine Learning Models for Structural Power Estimation,” IEEE Access, vol. 13, pp. 11544–11555, 2025.
M. Alam, R. Gupta, and S. Kundu, “Neural Network-Based Power Estimation Using Switching Activity,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1–5.
T. Nguyen, A. Tran, and P. Pham, “Switching Activity Driven Power Estimation Using SVR,” IEEE Access, vol. 9, pp. 102345–102356, 2021.
S. Gupta, M. Verma, and K. Roy, “Temporal Power Modeling Using LSTM Networks,” in Proc. Design, Automation & Test in Europe (DATE), 2022, pp. 1–6.
H. Kim, J. Lee, and Y. Park, “CNN-Based Encoding of Switching Activity for Power Estimation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 10, pp. 3951–3962, 2022.
P. Das and R. Sen, “Probabilistic Switching Activity Modeling Using Machine Learning,” Microprocessors and Microsystems, vol. 92, pp. 104605, 2023.
Y. Zhou, S. Liu, and J. Wu, “Attention-Based Power Estimation from Switching Traces,” IEEE Access, vol. 11, pp. 55678–55689, 2023.
K. Verma, A. Jain, and R. Gupta, “Hybrid CNN–LSTM Model for Power Estimation in CMOS Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, no. 9, pp. 2861–2872, 2024.
A. Ibrahim and H. Saleh, “Lightweight Regression Models for Switching Activity Power Prediction,” Microprocessors and Microsystems, vol. 98, pp. 104788, 2024.
J. Lee, S. Park, and M. Kim, “Self-Supervised Learning for Power Estimation Using Switching Activity,” in Proc. Design, Automation & Test in Europe (DATE), 2025, pp. 1–6.
S. Bansal, R. Mehta, and A. Verma, “Reinforcement Learning–Assisted Feature Selection for Power Estimation,” IEEE Access, vol. 13, pp. 45211–45223, 2025.
K. Sato, T. Yamada, and H. Nakamura, “PVT-Aware Power Estimation Using Regression Models,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 7, pp. 1401–1412, 2021.
M. Hassan, A. Rahman, and S. Islam, “Leakage Power Modeling Across Technology Nodes Using SVR,” IEEE Access, vol. 9, pp. 118902–118913, 2021.
V. Reddy, S. Mishra, and P. Chakrabarti, “Deep Learning-Based Power Estimation with Process Variation Awareness,” Integration, the VLSI Journal, vol. 81, pp. 45–55, 2022.
T. Morita, Y. Tanaka, and K. Ito, “Bayesian and Deep Learning Models for Process-Variation-Aware Power Estimation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 12, pp. 4689–4700, 2022.
P. Singh, R. Sharma, and M. Gupta, “Uncertainty-Aware Power Estimation Using Gaussian Process Regression,” Microelectronics Journal, vol. 132, pp. 105404, 2023.
D. Kwon and S. Kang, “Aging-Aware Power Estimation Using Machine Learning,” IEEE Access, vol. 11, pp. 89211–89222, 2023.
R. Yadav, N. Joshi, and P. Kulkarni, “Multi-Task Learning for Dynamic and Leakage Power Estimation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, no. 6, pp. 1684–1696, 2024.
F. Omar, A. Khalil, and M. Abouelatta, “Physics-Informed Neural Networks for Accurate Power Modeling,” in Proc. Design, Automation & Test in Europe (DATE), 2024, pp. 1–6.
Y. Liu, J. Zhang, and H. Yang, “Cross-Technology Transfer Learning for Power Estimation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 44, no. 3, pp. 823–835, 2025.
S. Nair, P. Kulkarni, and A. Deshpande, “Transformer-Based Scaling-Aware Power Estimation for Advanced CMOS Nodes,” in Proc. Design Automation Conference (DAC), 2025, pp. 1–6.
S. Ramesh, K. Balaji, and R. Venkatesan, “RTL-Level Power Estimation of CMOS VLSI Circuits Using Multivariate Linear Regression,” IEEE Access, vol. 9, pp. 112345–112356, 2021.
Y. Zhou, L. Chen, and M. Zhang, “Nonlinear Polynomial Regression for Gate-Level Power Estimation in CMOS VLSI Designs,” Integration, the VLSI Journal, vol. 78, pp. 101–110, 2021.
A. Mehta and N. Patel, “Regularized Linear Regression Techniques for Accurate Power Modeling of Digital Circuits,” Microelectronics Journal, vol. 120, pp. 105056, 2022.
R. Kumar, P. Singh, and A. Verma, “Support Vector Regression-Based Power Estimation Using Switching Activity and Structural Features,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 11, pp. 4213–4224, 2022.
H. Wang, J. Liu, and X. Li, “Leakage Power Estimation of CMOS Circuits Using SVR and Process Parameters,” IEEE Access, vol. 10, pp. 98432–98443, 2022.
P. Singh, R. Sharma, and M. Gupta, “Comparative Analysis of Linear, Polynomial, and SVR Models for VLSI Power Estimation,” in Proc. Design, Automation & Test in Europe (DATE), 2023, pp. 1–6.
J. Almeida, T. Rodrigues, and F. Silva, “Kernel Ridge Regression for Post-Synthesis Power Modeling of CMOS VLSI Circuits,” Integration, the VLSI Journal, vol. 86, pp. 21–30, 2023.
S. Choi, Y. Kim, and H. Park, “Early-Stage Power Estimation Using Epsilon-Support Vector Regression,” IEEE Access, vol. 11, pp. 76544–76555, 2023.
M. Rahman, A. Hasan, and S. Uddin, “Normalized Nonlinear Regression Models for Workload-Aware Power Estimation,” Microprocessors and Microsystems, vol. 98, pp. 104786, 2024.
M. O. Nusrat, M. R. Amin, and S. Ahmed, “Explainable Regression Baselines for Machine Learning–Based Prediction Models,” arXiv preprint arXiv:2403.11245, 2024.
R. Iyer, S. Kannan, and P. Narayanan, “Multi-Output Support Vector Regression for Dynamic and Leakage Power Estimation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, no. 8, pp. 2567–2578, 2024.
X. Huang, Z. Li, and Y. Sun, “PVT-Aware Nonlinear Regression Models for Robust Power Estimation in Advanced CMOS Nodes,” IEEE Access, vol. 12, pp. 33421–33433, 2024.
A. Verma, K. Mishra, and R. Gupta, “Transfer Learning–Assisted SVR for Cross-Technology Power Estimation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 44, no. 2, pp. 589–601, 2025.
D. Lopez, M. Fernandez, and J. Cruz, “Sparse Nonlinear Regression Models for Lightweight Power Estimation in VLSI Circuits,” Integration, the VLSI Journal, vol. 91, pp. 102–111, 2025.
S. Nair, P. Kulkarni, and A. Deshpande, “Unified Benchmarking of Regression-Based Machine Learning Models for CMOS Power Estimation,” in Proc. Design Automation Conference (DAC), 2025, pp. 1–6.
Downloads
How to Cite
Issue
Section
License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
