A Hybrid Stacked Machine Learning Framework for Accurate Power Estimation in CMOS VLSI Circuits
Keywords:
CMOS VLSI, Power Estimation, Machine Learning, Random Forest, XGBoost, Backpropagation Neural Network, Stacked EnsembleAbstract
In the design of CMOS VLSI circuits, accurate power estimation is one of the major hurdles, since it directly determines the performance, reliability, and energy efficiency of the latest integrated circuits. The techniques of the conventional analytical and empirical power estimations often miss the nonlinear relationships between circuit parameters that capture the complexity of the circuit, thus causing the circuit designer to make wrong predictions during the early stages of the circuit design. To overcome these hurdles, this paper introduces a hybrid stacked machine learning framework for accurate power estimation in CMOS VLSI circuits. The method suggested integrates Random Forest (RF) and XGBoost models for efficient feature selection and importance analysis, which in turn recognizes the major circuit attributes (like logic gate count, flip-flops, and combinational elements) that profoundly affect power consumption. The reduced set of features is then given to a Backpropagation Neural Network (BPNN) that learns the highly complex nonlinear relationships between circuit parameters and power dissipation. On top of that, a meta-learning strategy that leverages linear regression is used to blend the predictions from RF, XGBoost, and BPNN, resulting in a stacked ensemble that is more accurate and reliable than any of the individual ones. The framework is tested on the ISCAS’89 benchmark circuits and its performance is analyzed using Mean Squared Error (MSE), Root Mean Squared Error (RMSE), and R² score, which are the standard metrics of performance evaluation. The findings from the experiments indicate that the stacked model proposed by the authors surpasses the individual models significantly, in terms of predicting power more accurately, less error in estimation, and more generalization across different circuit configurations. Thus, the hybrid machine learning-based power estimation framework supports power budgeting and optimization in the early stages of design, which ultimately leads to energy-efficient CMOS VLSI design and low-power future integrated circuits.
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