High Speed Energy-Efficient Carry Skip Adder High-Speed skips logic at different levels- A Review
Keywords:
Carry skip adder (CSKA), energy efficient, high performance, hybrid variable latency adders, voltage scalingAbstract
In this paper, survey on a carry skip adder (CSKA) structure that contains a higher speed however lower energy consumption compared with the standard one. The speed improvement is achieved by applying concatenation and inculpation schemes to enhance the efficiency of the conventional CSKA (Conv-CSKA) structure. The projected hybrid variable latency CSKA reveal reduction within the power consumption compared with the most recent works during this field whereas having a reasonably high speed.
References
Milad Bahadori, Mehdi Kamal, Ali Afzali-Kusha, “High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015.
Yajuan He, Chip-Hong Chang, “A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary To Two’s Complement Converter”, IEEE Transactions on Circuits and Systems—I: Regular Papers, Vol. 55, No. 1, February 2008.
Dejan Markovic, Cheng C. Wang, Louis P. Alarcón, “Ultralow-Power Design in Near-Threshold Region”, IEEE, March 2010.
Ronald G. Dreslinski, Michael Wieckowski, David Blaauw, “Near-Threshold Computing: Reclaiming Moore’s Law Through Energy Efficient Integrated Circuits”, IEEE Vol. 98, 2010, IEEE No. 2, February 2010.
Shailendra Jain, Surhud Khare, Satish Yada, Ambili V, “A 280mV-to-1.2V Wide-Operating-Range IA-32 Processor in 32nm CMOS”, IEEE International Solid-State Circuits Conference, February 2012.
I. Koren, Computer Arithmetic Algorithms, 2nd ed., Natick, MA, USA: A K Peters Ltd., 2002.
R. Zlatanovici, S. Kao, B. Nikolic, “Energy-delay optimization of 64-bit carry-lookahead adders with a 240 ps 90 nm CMOS design example”, IEEE J. Solid-State Circuits, Vol. 44, No. 2, pp. 569–583, February 2009.
S. K. Mathew, M. A. Anders, B. Bloechel, T. Nguyen, R. K. Krishnamurthy, S. Borkar, “A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS”, IEEE J. Solid-State Circuits, Vol. 40, No. 1, pp. 44–51, January 2005.
V. G. Oklobdzija, B. R. Zeydel, H. Q. Dao, S. Mathew, R. Krishnamurthy, “Comparison of high-performance VLSI adders in the energy-delay space”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 6, pp. 754–758, June 2005.
B. Ramkumar, H. M. Kittur, “Low-power and area-efficient carry select adder”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 2, pp. 371–375, February 2012.
M. Vratonjic, B. R. Zeydel, V. G. Oklobdzija, “Low- and ultra-low power arithmetic units: Design and comparison”, in Proceedings of the IEEE International Conference on Computer Design, VLSI Computer Processes (ICCD), October 2005, pp. 249–252.
C. Nagendra, M. J. Irwin, R. M. Owens, “Area-time-power tradeoffs in parallel adders”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 43, No. 10, pp. 689–702, October 1996.
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