VLSI Architecture for Universal Shift Register using DFF based on PG and FG Reversible Gate
Keywords:
Serial in Serial Output (SISO), Serial in parallel out (SIPO), Parallel in Serial out (PISO), Parallel in Parallel out (PIPO), Maximum FrequencyAbstract
Over the last few decades, reversible logic system/circuits have received considerable attention in the diversified fields such as nanotechnology, quantum computing, cryptography, optical computing and low power design of VLSI circuits due to their low power dissipation characteristics. In this paper, we proposed the design of reversible shift register (SR) i.e. serial-in-serial out (SISO), serial-in-parallel out (SIPO), parallel-in-serial out (PISO), parallel-in-parallel out (PIPO) SR and universal shift register using reversible D_FF. The D_FF is consisting of reversible PG and FG gate. The all design is implemented Xilinx software, VHDL language and calculated different parameter i.e. number of slice, number of look up table and maximum combinational path delay.
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