Study And Review Of Designing Sense Amplifiers For Dram Using CMOS Process
Keywords:
Sense Amplifiers, DRAM, FFT, CMOS Memories, Sense amplifier interfacingAbstract
This paper presents study and review of designing and analysis for CMOS sense amplifiers for dynamic and static memories. Sense amplifiers in association with semiconductor memories are the key elements in defining the overall performance of CMOS memories. The studied designs are implemented using CMOS process technology using BSIM-4 Spice models for both open book and closed book architectures. The design includes circuit and operation descriptions, transient signal analysis, FFT analysis, also evaluation of magnitude, phase, and group delay is done at range frequency range from 100 MHz to few GHz. The paper also studies and review a physical design and interfacing logic for interfacing DRAM Memory arrays to Sense amplifiers and operating point analysis for the same.
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