Dual-Tox 7T SRAM Cell Design for Leakage Power Reduction on 45nm Technology
Keywords:
SRAM Cell, Power Reductio, CMOS technologyAbstract
This paper presents techniques based on dual oxide thickness assignment to reduce the leakage power of SRAM but maintaining their performance. The proposed a new seven transistors (7T) dual oxide thickness SRAM cell is proposed in this paper for simultaneously reducing the active and standby mode power consumption while enhancing the data stability and the read speed. With the new 7T SRAM cell, the storage nodes are isolated from the bit lines during a read operation, thereby enhancing the data stability as compared to the standard six transistors (6T) SRAM circuits. The transistors of the cross-coupled inverters are not on the critical read delay path with the new technique. Minimum sized dual-oxide thickness transistors are therefore conveniently used in the cross-coupled inverters for significantly reducing the leakage power consumption without causing degradation in the read speed. With the proposed 7T SRAM circuit, the static noise margin and the read speed are enhanced by up to 83% and 15%, respectively, as compared to the conventional 6T SRAM circuits. Furthermore, the leakage and the write power consumptions of the proposed dual-Tox SRAM circuit are reduced by up to 76% as compared to the conventional 6T SRAM circuits in a 45nm CMOS technology.
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