Aditya Pratap Singh, Prof. Satyarth Tiwari (2020) “Design, Implementation and Fast Fourier Analysis of Digital Locked loops for clock generation using C5 SCMOS”, International Journal of Research & Technology, 8(4), pp. 85–90. Available at: https://ijrt.org/j/article/view/528 (Accessed: 10 June 2026).