ADITYA PRATAP SINGH, PROF. SATYARTH TIWARI. Design, Implementation and Fast Fourier Analysis of Digital Locked loops for clock generation using C5 SCMOS. International Journal of Research & Technology, [S. l.], v. 8, n. 4, p. 85–90, 2020. Disponível em: https://ijrt.org/j/article/view/528. Acesso em: 15 may. 2026.