SACHINDRA PATHAK,PROF. MANISH SAXENA. Minimum Path Delay of SP and DP Floating Point Multiplier using Parallel Multiplier Technique. International Journal of Research & Technology, [S. l.], v. 10, n. 1, p. 60–64, 2022. Disponível em: https://ijrt.org/j/article/view/448. Acesso em: 26 oct. 2025.